On June 16, 2026 the U.S. Patent and Trademark Office issued U.S. Patent No. 12,660,703 B2 to Advanced Micro Devices, Inc., titled "3D layout and organization for enhancement of modern memory systems." The grant matters because of where AMD sits in the AI-compute stack: it is the credible number-two in datacenter accelerators, and the bottleneck for accelerators is no longer raw logic but the memory feeding it. A patent on how to physically organize stacked memory dies is a patent on bandwidth, and bandwidth is the currency of the AI buildout.
The named inventors are Divya Madapusi Srinivas Prasad, Vignesh Adhinarayanan, Michael Ignatowski, and Hyung-Dong Lee. The classification is compact and telling: alongside the wafer-level stacking code H10W 90/00 sits G11C 11/4097, a digital-memory subclass — meaning the grant is read at the intersection of 3D die stacking and DRAM array organization, exactly the H10W/G11C overlap where stacked-memory IP concentrates.
"Bitlines are routed through the first and second IC dies in a substantially vertical orientation."— U.S. Patent No. 12660703, source
The central idea in the abstract is a reorientation of the bitline. In a conventional memory die, bitlines and wordlines are both planar — they run horizontally across the array within a single die, and the array is read by selecting the intersection of one wordline and one bitline. AMD's described stack keeps the wordlines planar but lifts the bitline into the third dimension. The abstract states a first memory IC die and a second memory IC die stacked on it, with bitlines "routed through the first and second IC dies in a substantially vertical orientation," while "wordlines within the first memory IC die are oriented orthogonal to the bitlines." The bitline, in this scheme, is no longer a wire living inside one die; it is a vertical column threading both stacked dies.
The structural claim: a bitline that spans the stack
That vertical bitline is the element a competitive read should anchor on. Stacking memory dies is, by 2026, ordinary — flash and DRAM vendors have shipped vertically stacked, bonded dies for years, and high-bandwidth memory is itself a stack of DRAM dies over a logic base. What is less ordinary is routing the bitline itself vertically through the stack so that cells in the second die share the substantially vertical bitline with cells in the first die. The patent foregrounds that orientation: substantially vertical bitlines, orthogonal planar wordlines. The geometry is the invention.
Why reorient the bitline at all? The abstract frames the goal as enhancement of modern memory systems, and the structural logic follows the same pressure that drives every 3D memory effort: bitline length and the parasitic load it carries. A long planar bitline accumulates capacitance, which slows the sense operation and burns energy on every access. By routing the bitline vertically through stacked dies rather than stretching it across the plane of a single large array, the design can change the trade-off between array density and bitline loading — more cells served per bitline footprint, with the connection riding the short vertical dimension of the stack rather than the long horizontal dimension of the die. The orthogonal wordline arrangement is what keeps each cell individually addressable once the bitline goes vertical.
Where it sits in AMD's memory-architecture portfolio
AMD does not fabricate its own DRAM, which makes a memory-organization grant a notable entry in its portfolio. The company's interest is architectural: as the designer of accelerators and the packages that integrate compute and memory, AMD has a direct stake in how stacked memory is organized at the die level, even when the cells themselves are built by a memory partner. This grant — vertical bitlines spanning stacked memory dies — reads as system-architecture IP staking out how AMD believes high-density memory should be physically organized to feed compute, not as a fab-process claim. It sits alongside AMD's broader die-stacking activity (the same June 16 grant drop includes an AMD patent on die stacking for modular parallel processors, US 12,660,682) and reinforces a portfolio posture centered on 3D integration as the lever for memory bandwidth.
For the thicket map, the takeaway is the orientation flag. Vertical bitlines through stacked dies, with orthogonal planar wordlines, is a specific geometric commitment, and US 12,660,703 plants AMD's marker on it. As with any abstract-level read, the enforceable boundary lives in the independent claim and its dependents — the abstract tells you the invention is centered on the vertical-bitline-plus-orthogonal-wordline stack, but the claim language will fix exactly what is required (how many dies, what the routing structure must include, how the cells couple to the vertical bitline). What the record establishes today is direction: in the contest over how to physically organize the memory that AI accelerators are starving for, AMD has filed and now holds a claim on lifting the bitline out of the plane.