Grant Watch · Lead record
A grant issued June 16, 2026 to AMD describes stacking memory dies with bitlines routed vertically through both dies and wordlines running orthogonal to them. A claim-level read of the 3D memory layout.
Grant Watch
A grant issued June 16, 2026 to IBM describes routing one transistor's signal from the front side and the other's power from the back side of a CFET-style stacked device. Here is what the record actually claims.
Regulatory Docket
A January 2026 BIS rule moves a defined band of accelerators to case-by-case review, gated by precise thresholds and a mandatory U.S. third-party testing certification.
Regulatory Docket
A September 2025 BIS rule makes any entity 50 percent owned, in aggregate, by listed parties automatically restricted. It mirrors Treasury's model and reshapes diligence for the chip supply chain.
Regulatory Docket
The AI Diffusion framework controls closed-weight model parameters with a benchmark-relative threshold and sorts destinations into three tiers with cumulative TPP ceilings. The technical scope, decoded.
Regulatory Docket
The 2023 BIS rule folded advanced-node tool entry 3B090 into 3B001 and 3B002 and pinned the controls to specific process physics. Here is what those entries actually require.
Regulatory Docket
The advanced-computing rule reaches the memory layer with a single metric: greater than 2 GB/s per square millimeter. A second figure, 3.3, gates License Exception HBM. Here is the technical logic.
Regulatory Docket
BIS does not measure AI chips by nanometers in the advanced-computing rule. It measures them by Total Processing Performance and performance density. Here is exactly where the cutoffs sit.
Claim Construction
As chips get wired from both sides, new failure modes appear — and so do new claims. IBM's June 2026 double-sided IC grant shows the electrostatic guard ring is the limitation doing the work.
From Claim to Market
Compute density is now a heat problem, and heat is becoming patent territory. TSMC's liquid-cooled lid and Samsung's heat-dissipation grants show thermal IP moving onto the commercial critical path.
From Claim to Market
The advanced-packaging boom has a paper trail older than the hype. Tracing a 2017 Micron interposer grant to the 2026 fan-out packages shows how early IP positions cash in.
Thicket Map
Memory density now scales up, not out. Two June 2026 grants show the split between vertically stacked transistor-storage cells (Micron) and a full monolithic 3D fabrication route (Monolithic 3D Inc.).
Portfolio Profile
Integrated fan-out is how TSMC turned packaging into a competitive moat. Three June 2026 grants — RDL design, package structure, and dielectric method — show a portfolio engineered for breadth.
Claim Construction
SRAM scaling is where logic-node bragging rights are won. A June 2026 TSMC grant on an SRAM middle strap with a feedthrough via shows how granular — and how routing-specific — leading-edge memory-cell IP has become.
Claim Construction
ASML builds the EUV scanner, but the patentable process around it is wide open. Two June 2026 grants — a pattern-formation method and a vacuum-bake step — show where foundries and tool makers actually claim scope.
Thicket Map
The chiplet era runs on die-to-die links. The interesting June 2026 grants are not from the foundries — they are from specialists claiming the bandwidth-balancing and connectivity-monitoring layers UCIe leaves open.
Portfolio Profile
HBM's bandwidth is a packaging achievement as much as a memory one. Intel and Samsung's June 2026 grants show where the stacking, power, and thermal IP actually concentrates.
Thicket Map
Hybrid bonding is the connective tissue of advanced packaging. The June 2026 grants show three assignees claiming three non-overlapping pieces — passive devices, barrier metallurgy, and the stacked-structure interface.
Claim Construction
Backside power is the headline; the backside contact is the limitation that matters. Two June 2026 grants show how narrowly — and how differently — each assignee claims the connection.
Thicket Map
Two foundries, two strategies, one transistor architecture. Reading the June 2026 nanosheet grants shows the thicket is built around buried power and parasitic control, not the channel itself.
Claim Construction
A patent titled merely 'SRAM structures' hides a specific claim. TSMC's late-2025 grant narrows to a particular cell built in the H10B taxonomy.
Claim Construction
The research institute that originates device concepts patents them too. imec's late-2025 grant claims multiport memory cells using stacked active layers.
Claim Construction
Adeia keeps extending its hybrid-bonding franchise. A mid-2025 grant claims a conductive barrier in the direct bond - another licensable refinement.
Claim Construction
Adeia's bonding IP reaches into image sensors too. A mid-2025 grant claims stacked-device fabrication spanning the H10F photodevice classes.
