Claims Brief · Lead record
The vacuum evaporation step is the limitation carrying claim 1. The third independent claim relocates the optical structure from the wafer to the chip, and the published record supports both readings only separately.
Claims Brief
US20260204307A1, published July 16, 2026, is directed to updating usage-based-disturbance data for two or more concurrently refreshed DRAM rows one procedure at a time, inside a single refresh interval. It is a pending application, not a grant.
Claims Brief
US20260206525A1, published July 16, 2026 and assigned to ASML NETHERLANDS B.V., claims an apparatus that parks donor dies in machined recesses and pre-aligns the whole population before a single relative stage move. Claim 1 recites a target-measurement step that the application's abstract does not describe.
Claims Brief
Huawei's July 16 publications run to 52 records, and 51 of them are radios, antennas, handsets and software. The odd one out claims an SRAM array with its NFETs moved into a back-end-of-line device layer.
Claims Brief
A pending TSMC application claims a sequence — front-side silicide first, then a back-side implant and a nanosecond laser anneal — with the ordering written into claim 1 itself. Claim 11 recites the same idea around a nanostructure device.
Claims Brief
A published application walks a two-liner structure for taming stress in through-glass vias, keyed to a Young's-modulus split between the inner and outer materials. It is pending, not granted.
Claims Brief
A published application in this week's drop claims a CMOS pair whose two gate-all-around stacks are non-coplanar — and whose dependent claims reach mixed channel materials and unequal sheet counts. It sits inside a cluster of backside-contact filings, all classified under the reorganized H10D device subclasses.
Claims Brief
An issued Intel grant is directed to an interconnect bridge set on the upper surface of a through-glass-via layer and surrounded by co-planar mold, with two dies bridged across it. The independent claim ties the component, the mold planarization, and the conductive pillar together; it is a granted patent, not a pending application.
Claims Brief
A Samsung (005930.KS) application in this week's publication drop is directed to a two-transistor memory cell whose transistors are stacked on each other and share a vertically running bit line. The independent claim ties a silicon-channel access transistor to an oxide-semiconductor storage transistor, classified under the H10B 12/00 DRAM subclass.
Claims Brief
High-bandwidth memory stacks DRAM core dies on a base die linked by through-silicon vias. A 2026 Samsung claim shows where the IP is moving, and CPC H01L 25/0657 classifies the stack.
Patent Landscape
High-numerical-aperture EUV scanners use anamorphic optics that demagnify unequally in two directions. Here is what an ASML granted claim recites about that, and how it is classified under CPC G03F 7/705.
Claims Brief
Hybrid bonding joins dies with simultaneous metal-to-metal and dielectric-to-dielectric bonds. Here is what a granted TSMC claim recites and how the method is classified under CPC H01L 24/80.
Claims Brief
Backside power delivery network (BSPDN) designs move the power rails beneath the wafer. Here is what a granted buried-power-rail claim recites and how the structure is classified.
Patent Landscape
Gate-all-around nanosheet transistors are the leading-edge logic device replacing the FinFET. This is what the granted claims actually recite and where they sit in the CPC scheme.
Claims Brief
A patent issued to Taiwan Semiconductor Manufacturing (TSMC) on June 23, 2026 claims a multi-dimension through-silicon-via structure in which a wider columnar via carries power and conducts heat while a narrower via handles low-capacitance signaling. The granted claims tie the via pattern to backside alignment, classified under the H10W 3D-IC subclasses.
CPC Field Guide
H01L is the Cooperative Patent Classification subclass for semiconductor devices and their manufacture. This is what the code covers, how its groups are organized, and how to read it on a real patent.
Research Brief
A new arXiv preprint describes ExSpike, an FPGA neuromorphic architecture that keeps every spiking-network layer event-driven and reports up to 10x higher per-PE energy efficiency than a prior FPGA SNN accelerator.
Research Brief
A new arXiv study characterizes an interference phenomenon in processing-using-DRAM across 96 real DDR4 chips, reporting that data in concurrently computing columns can shift in-DRAM compute outputs by as much as 48 percent.
Claims Brief
A Samsung (005930.KS) application published in this week's drop is directed to a copper-pad bonding structure whose claim hinges on a specific mean grain size. It sits inside a cluster of stacked-package filings, classified under the new H10W bonding subclasses.
Research Brief
Sliding ferroelectrics promise low-barrier switching for non-volatile memory. A June 2026 preprint shows that making them superlubric changes the physics entirely, producing a hybrid electronic-ionic polarization and exotic hysteresis.
Research Brief
Quantum-computing control electronics live at cryogenic temperatures, where transistor models must be exact. A June 2026 preprint locates an intrinsic channel-impedance dispersion deep in strong inversion and pins it on impurity-induced hopping.
Research Brief
Power and performance have decades of modeling tools behind them. A June 2026 preprint argues carbon now needs the same treatment, and ships an extensible tool to bring it into architectural design-space exploration.
Research Brief
Continuous-time neural predictors map badly onto matrix-multiply hardware. A June 2026 preprint maps them instead onto multi-bit ferrodiodes, claiming a first end-to-end ferroelectric compute-in-memory neuromorphic system.
Research Brief
Fine-grain clock gating is one of the oldest dynamic-power tricks in RTL, and one of the most stubbornly manual. A June 2026 preprint pairs ML waveform clustering with LLM code rewriting to automate it across industrial-scale designs.
