The record at the center of this brief, US20260198346A1, is a published application — it was published on July 9, 2026 and remains pending. It has not issued as a patent, so its claims describe what is being sought, not coverage that has been granted. That status matters for how the independent claim should be read: it defines the boundary the applicant is pursuing, and it can still change during examination.

The subject matter is a through-glass via, or TGV — a conductive path punched vertically through a glass layer to route signals between the two faces of a package substrate. Glass cores have drawn sustained interest as an advanced-packaging medium, but glass and the metal filling a via expand and contract at different rates. That mismatch concentrates thermomechanical stress at the interface between the via metal and the surrounding glass. The application is directed to managing that stress with liner materials rather than by changing the via metal or the glass itself.

Walking the independent claim

Independent claim 1 is written as a microelectronic assembly built from a short list of elements. It recites a glass layer with a first surface and an opposing second surface; a via extending through that glass layer between the two surfaces, the via including a conductive material; a first liner on the sidewall of the glass in the via; and a second liner positioned between at least a portion of the first liner and the conductive material. The two liners are each an inorganic material, and the claim ties them together through a single distinguishing relationship: the second liner has a Young's modulus that is less than the first liner's.

A microelectronic assembly, comprising: a glass layer having a first surface and an opposing second surface; a via extending through the glass layer between the first surface and the second surface, the via including a conductive material; a first liner, on a sidewall of the glass layer in the via, including a first inorganic material having a first Young's modulus; and a second liner, between at least a portion of the first liner and the conductive material of the via, including a second inorganic material having a second Young's modulus that is less than the first Young's modulus.— MICROELECTRONIC ASSEMBLIES INCLUDING DOUBLE LINERS IN THROUGH-GLASS VIAS, US20260198346A1

The load-bearing limitation is that modulus split. In plain terms, the outer liner — the one touching the glass sidewall — is the stiffer of the two, and the inner liner, sitting against the via metal, is more compliant. The claim itself does not require specific numbers; it only requires that the inner material be less stiff than the outer one. The specification, however, discloses ranges that put that language in context: a first-liner Young's modulus between 25 and 50 gigapascals, and a second-liner modulus between 1 and less than 25 gigapascals. The abstract also identifies candidate chemistries, describing a first liner including silicon and oxygen and a second liner including silicon, oxygen, and carbon, optionally with fluorine. Those particulars appear in dependent claims and the disclosure rather than in the independent claim, which keeps its scope at the structural level.

The disclosure situates the structure with additional dimensional context that helps a reader picture what is claimed: via aspect ratios described from roughly 4:1 up to 30:1, and glass core thicknesses spanning about 50 micrometers to 2 millimeters. An IC-package embodiment is described in which the glass core carries the conductive via and the double-liner layer, framing the assembly as a packaging building block rather than a standalone component.

CPC context and the surrounding cohort

By subject matter, a double-liner through-glass via sits in the electrical-component and semiconductor-device packaging neighborhood of the CPC scheme — the H01L family that covers semiconductor devices and their interconnection and packaging, reaching arrangements for via structures and encapsulation within a substrate. The claim's emphasis on liner materials on a via sidewall places it among interconnect and via-formation art rather than among transistor-device claims.

The application published alongside a cohort of Intel packaging and integration records that issued the same week, and reading them together is useful for placing the pending claim in its field. Those siblings are granted patents — issued July 7, 2026 — not pending applications. US12677688B2 claims coaxial inductors fabricated through a drill-less via process on a glass substrate, with an hourglass-profile via opening filled with a magnetic layer — another glass-substrate via structure. US12677682B2 is directed to package metallization lines with a copper layer on a non-copper seed, aimed at die-to-die signaling, and US12677375B2 claims a stepped package and recessed circuit board. Two further grants reach adjacent integration territory: US12677699B2 on silicon-carbide power devices integrated with silicon logic, and US12676606B2 on transistor over-voltage protection.

Read as a group, the granted packaging claims and this pending via-liner application share a glass-core and advanced-packaging vocabulary. But the distinction in status is the point of a claims brief: the double-liner TGV structure described here is claimed in a document that is still under examination, while the surrounding via, metallization, and package claims are already issued. The independent claim's scope — a conductive through-glass via bracketed by a stiffer outer liner and a more compliant inner liner, separated by a Young's-modulus relationship — is what the applicant is asking the office to allow, and it should be read as a pending request rather than as settled coverage.