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Semiconductor IP
- Three Independents, One Floorplan, and an Abstract Limitation That Is Not Claimed
- Claim 1 is canceled and the wafer numbering never recovers
- Three independent claims that disagree about where the waveguide sits
- Micron application claims serialized counter updates inside the DRAM refresh window
- ASML Application Claims a Die-Placement Stage That Measures the Targets, Too
- Claim Construction: IBM's Double-Sided IC Patent and the Guard Ring Hiding the Real Claim
- From Claim to Market: The Thermal Patents Quietly Gating How Tall a Chip Stack Can Get
- From Claim to Market: A 2017 TSV-less Interposer Patent and What It Tells the 2026 Packaging Race
- The Vertical-Memory Thicket: Micron and Monolithic 3D Claim Different Routes to Stacked Density
- Portfolio Profile: TSMC's Fan-Out Packaging Patents Are a Wall, Not a Fence
- Claim Construction: What TSMC's SRAM 'Middle Strap' Patent Actually Claims
- Claim Construction: Reading TSMC's and Applied Materials' Latest EUV Process Patents
- Who Owns the Die-to-Die Interconnect? Eliyan and ProteanTecs Are Claiming Around UCIe
- Portfolio Profile: The Stacked-Memory Packaging Patents Behind the HBM Bottleneck
- The Hybrid-Bonding Thicket: Intel, TSMC, and SK hynix Are Fencing Different Layers
- Claim Construction: What IBM's and TSMC's Backside-Contact Patents Actually Cover
- The Gate-All-Around Thicket: Where IBM and TSMC's Nanosheet Patents Actually Land
- Claim Construction: TSMC's 2025 SRAM Structures Patent, Read Past the Generic Title
- Claim Construction: imec's Multiport Memory Cells With Stacked Active Layers
- From Claim to Market: Adeia's Conductive-Barrier Direct Hybrid Bonding
- From Claim to Market: Adeia's Stacked-Devices Fabrication Patent and the Sensor-Stacking Angle
- Claim Construction: IBM's Backside Transistor Integrated With a Backside Power Network
- Claim Construction: IBM's Stacked-FET SRAM and the CFET Path to Denser Memory
- From Claim to Market: Broadcom's Copper-Bonded Memory Stack Patent
- Claim Construction: TSMC's Interposer Directly Bonded to Multiple Dies
- Claim Construction: Intel's PHY-less Die-to-Die I/O and the UCIe-Era Interconnect
- Claim Construction: Intel's Composite Bridge Die-to-Die Interconnect
- Claim Construction: Intel's Interconnect Architecture Combining Silicon Interposer and EMIB
- Claim Construction: TSMC's Forksheet Transistor Structure, the Post-Nanosheet Device
- Claim Construction: Tokyo Electron's Three-Dimensional Memory Cell Structure
- Claim Construction: TSMC's 2023 Backside Interconnect Structure and the BSPDN Build-Out
- Claim Construction: Nanya's Buried Power Line and Buried Signal Line Method
- Claim Construction: Applied Materials' Low-Resistivity DRAM Buried Word-Line Stack
- From Claim to Market: Adeia's CMP-for-Hybrid-Bonding Patent and the Licensing Engine
- The Liaw Files: Mapping TSMC's 2022 FinFET SRAM Cell Portfolio
- Claim Construction: TSMC's EUV Mask Defect-Prevention Patent
- Claim Construction: TSMC's Multi-Chip Wafer-Level Package and the InFO Lineage
- Claim Construction: TSMC's Hybrid Structure With GAA and Stacked FinFET Devices
- Claim Construction: IBM's Enhanced Bottom Dielectric Isolation in Gate-All-Around Devices
- Claim Construction: TSMC's EUV Mask Anti-Carbon-Contamination Patent
- Claim Construction: TSMC's 2021 Backside Power Rail Patent and What It Actually Claims
- Claim Construction: TSMC's CoWoS Interposer With Programmable Capacitance Arrays
- Claim Construction: Kepler Computing's 3D-Integrated Ultra-High-Bandwidth Memory
- Claim Construction: Xilinx's Multi-Rank HBM Patent and the Bandwidth It Unlocks
- From Claim to Market: Invensas's Embedded Organic Interposer and the Licensing Behind It
- The EUV Light-Source Thicket: Who Owns the Plasma That Prints Sub-7nm
- Claim Construction: Apple's Fanout Interposer Chiplet for High-Density Interconnect
- Claim Construction: TSMC's High-Mobility Strained-Channel FinFET, Read Closely
- Claim Construction: IBM's Co-Integration of Non-Volatile Memory on Gate-All-Around
- Claim Construction: TSMC's Front-to-Back Bonding With Through-Substrate Vias
- Claim Construction: IBM's Multi-Threshold Gate-All-Around FET With Common Gates
- The 2020 TSV Portfolio: Who Owned Through-Silicon-Via IP Before HBM Went Mainstream
- Claim Construction: TSMC's 2020 Hybrid-Bonding Patent for Stacking Integrated Circuits
- Claim Construction: IBM's Microstructure Modulation for Metal Wafer-to-Wafer Bonding
- Claim Construction: IBM's Self-Limited Inner Spacer for Gate-All-Around Nanosheets
Semiconductors
- One Silicon Filing in a Drop of Fifty-Two
- Two Method Claims for Annealing a Wafer From Underneath
- Reading the Double-Liner Through-Glass-Via Claim
- What Intel's Newly Published Asymmetric-CMOS Application Actually Claims
- What Intel's Cavity-Less Glass-Core Interconnect Grant Actually Claims — and Note It Is Issued
- What Samsung's Newly Published 2T Memory-Cell Application Actually Claims: Two Stacked Transistors on a Vertical Bit Line
- HBM Stacked-DRAM Patents: Reading the Base-Die Claims Behind 3D Memory
- High-NA EUV Patents: Why the Claims Talk About Anamorphic Demagnification
- Hybrid-Bonding Patents: The Dual-Anneal Claim at the Heart of Advanced Packaging
- Backside Power Delivery Patents: Reading the Buried-Power-Rail Claims at CPC H01L 23/5286
- Gate-All-Around Nanosheet Patents: What the Claims Cover Under CPC H10D 30/6735
- What TSMC's Newly Granted Dual-Width TSV Patent Actually Claims: One Via for Power, Heat, and Backside Alignment
- What Is CPC Class H01L? The Semiconductor Patent Classification, Explained
- ExSpike: A Full-Event Neuromorphic FPGA Design Reports 281.85 GOPS/W on Spiking Networks
- PuDGhost: Real DDR4 Chips Show Up to 48% Output Corruption in Processing-Using-DRAM
- What Samsung's Newly Published Hybrid-Bonding Application Actually Claims: A 25-to-70-nm Grain Limit
- A New Class of Ferroelectric: How Sliding-Plus-Buckling Keeps Polarization Alive in Superlubric van der Waals Stacks
- Cryo-CMOS Has a Hidden Frequency Dispersion — and It Isn't the Parasitics
- Carbon as a Design Metric: ACT3 Wants Sustainability in the Loop Alongside Power and Performance
- FerroNDS Runs Neural Dynamical Systems on Ferroelectric Compute-in-Memory at Sub-Microjoule Energy
- AUTOGATE Puts an LLM Inside the Clock-Gating Loop — and Reports Double-Digit Power Cuts on NVDLA
- One Datapath for Three Bottlenecks: MIVE Folds Softmax, LayerNorm and RMSNorm Into a Single Integer Vector Engine
- AMD's Vertical-Bitline Memory Stack: What US 12,660,703 Claims About 3D DRAM Organization
- IBM's Stacked-Transistor Wiring Patent: Reading US 12,660,599 on Hybrid Signal-and-Power Tracks
- The H200 Rule: How BIS Drew a New Line at 21,000 TPP and 6,500 GB/s of DRAM Bandwidth
- The 50 Percent Affiliates Rule: How BIS Extended the Entity List to Unnamed Subsidiaries
- ECCN 4E091: How BIS Put AI Model Weights on the Control List, and Tiered the World to Enforce It
- 3B001 and 3B002: The Deposition Parameters and Node Definitions Behind the SME Controls
- ECCN 3A090.c: How BIS Wrote an HBM Control Around Bandwidth Density, Not Bandwidth
- Inside ECCN 3A090: How TPP and Performance Density Draw the Export-Control Line on AI Chips