The limitation that matters in any backside-power patent is rarely the power rail — it is the contact that reaches through the wafer to touch the transistor's source/drain from behind. Move your attention there and two June 2026 grants stop looking like duplicates and start looking like deliberately different fences.
Take International Business Machines Corporation's US12652849B2, "Backside contacts for stacked transistor structures with shifted channels" (issued 2026-06-09). Walk the title as if it were claim language, because it nearly is: "stacked transistor structures" and "shifted channels" are limiting. The grant is classified in H10D 64/254 and H10D 84/85 — complementary-FET / stacked-device territory. The scope is therefore not "a backside contact" in the abstract; it is a backside contact in a CFET-style stack where the upper and lower device channels are laterally offset. A single-tier device with aligned channels reads outside it. That offset is the design-around lever.
Now set it beside Taiwan Semiconductor Manufacturing Co., Ltd.'s US12652820B2, bluntly titled "Backside contact" (2026-06-09). Its classifications — H10D 30/62, H10D 30/024, H10P 14/3411 — point at the contact-to-source/drain structure and its formation, not at a particular stacking arrangement. On its face TSMC is reaching for the more general structure. But "more general title" does not mean "broader claim": the enforceable scope is whatever the independent claim's element list actually recites, and a broad title routinely sits over a narrowly limited claim. The construction question is which fabrication-specific limitations — liner, etch-stop, self-alignment to a backside via — the independent claim requires.
Here is the limitation that decides infringement in both: self-alignment. A backside contact that is independently patterned and aligned to the front-side source/drain is one thing; a contact that is self-aligned to a sacrificial placeholder revealed from the back side is another. The economic value — and the hardest design-around — is in the self-aligned variant, because it tolerates the overlay error that wafer-thinning introduces. Read the dependent claims for where self-alignment is recited; that is where scope concentrates.
The design-around space follows directly. To avoid IBM's grant, you either un-stack the devices or align the channels — both costly. To avoid TSMC's, you change the contact-formation route the independent claim recites, which may be feasible if its claim is tied to a specific liner or etch-stop sequence. Neither is a paper tiger, but they fail for opposite reasons: IBM's scope is narrow by architecture, TSMC's by process.
The takeaway for claim-construction purposes: "backside power delivery" is a marketing category, not a claim. The patents live or die on the backside contact, and within that, on whether the independent claim recites a stacked/shifted-channel context (IBM) or a particular contact-formation method (TSMC). Construe those limitations first; the power rail is downstream.