An EUV mask is reused for every wafer in a production lot, so a single defect on the mask repeats on hundreds of wafers - one of the most expensive failure modes in the fab. Preventing mask defects is therefore high-value yield engineering. Taiwan Semiconductor Manufacturing Co., Ltd.'s mid-2022 grant claims a defect-prevention approach.
US11402743B2, "Mask defect prevention" (issued 2022-08-02), is classified across the EUV-mask subclasses G03F 1/24 with G03F 1/36, 1/38, 1/54, and 1/64, plus G03F 7/2004. The breadth of mask-related CPC codes signals a claim spanning mask design and handling aimed at preventing defects before they reach the wafer.
Construe the prevention limitation. The claim cannot be on 'defect-free masks' as an aspiration; it must specify a method or structure - a particular mask layout rule, a handling or inspection step, a protective feature - that prevents a defect mechanism. The independent claim's specifics are what is fenced.
The design-around space is the prevention mechanism. EUV mask defectivity is attacked many ways: pellicles, inspection-and-repair, mask-handling protocols, and design-for-manufacturability rules. A competitor using a different prevention route reaches comparable yield outside a claim tied to TSMC's specific approach.
This is operational yield IP - the kind a foundry generates from running the technology at the highest volume in the world. TSMC's EUV mask patents from this period (anti-contamination, defect prevention, radiation modification) collectively encode hard-won fab experience into defensible claims, which is part of how the foundry converts its operational lead into IP.
For a claim-construction read, mask-yield patents reward looking past the generic title to the specific defect mechanism addressed. 'Mask defect prevention' fences one prevention method; identifying which one is the whole exercise, and it determines whether a competing EUV program is anywhere near the claim.