US20260231831A1 published on August 6, 2026, assigned to Intel Corporation and naming ten inventors. It carries twenty claims, three of them independent: claim 1 and claim 8, both to a microelectronic assembly, and claim 14, to a method of fabricating one. The application is classified principally in H10W — the packaging and assembly range for semiconductor devices — with H10W 90/00, 90/724, 90/734, 90/736 and 90/794 among the codes on the record, alongside H10B 80/00 and several H10W 70-series and 74-series entries.

Claim 1 builds from the substrate up. It recites a package substrate; a first redistribution layer coupled to its top side by first interconnects; underfill between that RDL and the substrate; then a first, second and third die over the RDL, with the second laterally between and spaced apart from the other two. The scope-defining detail arrives next.

a first die, a second die, and a third die over the first RDL, the second die laterally between and spaced apart from the first die and the third die, and the first die and the third die having through silicon vias (TSVs) therein— HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE FIRST APPROACH, US20260231831A1

Two of the three lower dies carry through-silicon vias; the middle one does not. That asymmetry is recited, not optional. A structure in which all three carry TSVs, or in which the middle one does and the outer two do not, is outside the literal terms of the claim. The claim then adds a first insulating material around the three dies and conductive pillars within it, laterally spaced from all three and having the same vertical thickness as the insulating material — the limitation that makes the pillars a full-height path between the first redistribution layer and the second one recited above them.

What the top tier requires

Claim 1 continues into the compute tier with four named components, each with its own interconnect set and each laterally spaced from its neighbour: a first high bandwidth memory over the first die; a first graphics processor unit die over the first and second dies; a second GPU die over the second and third dies; and a second HBM over the third die. A second insulating material sits between each of those four and the second RDL, and along their sides. Read literally, claim 1 is directed to a four-component top tier in a memory-compute-compute-memory order, with each GPU die straddling the middle bridge. It is not a claim to bridge packaging generally.

Claim 8 is where the generality comes back. It repeats claim 1's structure and substitutes “a first memory die” and “a second memory die” for the two HBM recitations, dropping the high-bandwidth-memory requirement while keeping the GPU dies named. Anyone comparing the two claims should watch the material ordinals, which shift. Claim 1 calls the material between the first RDL and the substrate an “underfill material” and then numbers the insulating materials first and second. Claim 8 calls that same layer a “first insulating material,” so its second and third insulating materials correspond to claim 1's first and second. The structures are congruent; the numbering is offset by one throughout.

Claim 14 is the method counterpart to claim 1, tracking it element for element with providing and forming steps in place of structural recitations, and retaining the HBM language. Its dependents 15 through 20 mirror claims 2 through 7. The result is that the twenty claims cover a narrow structural space three times over rather than covering three different ideas.

The dependent claims add little breadth and a good deal of precision. Claim 2 requires each of the three lower dies to be thinner than the insulating material surrounding them. Claim 3 places the first and third dies on the first redistribution layer, where claim 1 had said only that all three were over it. Claim 7 divides the conductive pillars into two subsets, one laterally between the first and second dies and one between the second and third — pillars threaded between the bridges rather than confined to the package perimeter. Claims 5 and 6 handle co-planarity: the two GPU dies share a top surface level, and that level differs from the tops of the two memory stacks.

The abstract-to-claim gap

The most quotable line in the document is in the abstract: the first surfaces of the second and third dies have a combined surface area between 3,000 square millimetres and 9,000 mm². That range is a meaningful technical statement — the top of it is well past a single reticle field. It is also absent from all twenty claims. So is the abstract's entire framing, which describes generic first, second and third dies distributed across a first and second layer with an RDL between them, without a package substrate, without pillars, and without naming a GPU or a memory stack. The abstract and the claims are not describing the same breadth, and a reader who takes the area range as claimed scope will be wrong about what this application covers.

Two smaller drafting features are worth logging. Claims 4, 11 and 17 refer to “a top of the first GPU” and “a top of the second GPU,” while the antecedents introduced earlier in each claim are the first and second GPU die. And claim 12 in the claim 8 family compresses into one claim what claims 5 and 6 split across two in the claim 1 family — same co-planarity requirement between the GPU dies, same requirement that the memory tops sit at a different level, differently packaged.

Context for the filing: Intel published sixteen applications on August 6, of which a disaggregated-package application and a shared-metallization chiplet application occupy adjacent ground, and a die-to-die adapter and a clock-phase application address the same interface from the protocol side. This record is a pending application. Its claims are the applicant's opening position, and the scope described here is what was published, not what has been allowed.