Hybrid bonding only works if the two surfaces meeting at the bond are flat to within nanometers and the copper pads are recessed (dished) by a precise amount so they expand into contact on anneal. Achieving that surface is a chemical-mechanical polishing (CMP) problem. Adeia (formerly Invensas/Xperi), whose business is licensing rather than manufacturing, claims a CMP method for it in a 2023 grant.
US11552041B2, "Chemical mechanical polishing for hybrid bonding" (issued 2023-01-10, assignee Adeia Semiconductor Bonding Technologies Inc.), is classified in H01L 24/27 and 24/03/05/06 (bonding-area processing) with H01L 24/83 (bonding) and an extensive set of H01L 2224 dishing and surface subclasses. The claim is on the CMP process that prepares the bonding surface - the flatness and pad-recess control.
Construe the limitation as the polishing method, not the bond. The value is in the specific CMP sequence and the dishing profile it produces, which together determine whether the subsequent bond is void-free and electrically sound. The independent claim pins down the process parameters that matter.
The commercialization model is the story. Adeia does not bond wafers; it licenses the IP to foundries, OSATs, and memory makers who do - and hybrid bonding is now central to 3D-stacked logic and the latest NAND. Adeia's hybrid-bonding patents (the Ziptronix/Invensas lineage) are among the most-cited and most-licensed in the field.
That makes the CMP claim a high-value licensing asset rather than a blocking weapon. A company adopting hybrid bonding for HBM-base-die stacking or logic-on-logic is a royalty prospect; Adeia's posture is to be paid for the foundational surface-prep IP, not to exclude.
For an IP-risk reader, surface-preparation claims like this are easy to underweight because CMP sounds like a commodity step. But in hybrid bonding, surface prep is the bond, and Adeia's deep, early portfolio in this exact area is a recurring line item in the licensing budgets of everyone building 3D-stacked devices.