Micron Technology, Inc. is named as assignee on US20260204307A1, Performing Serialized Update Procedures during a Refresh Period, which published on July 16, 2026. The document is an A1 publication: a pending application that has been laid open, not an issued patent. Nothing in it has been examined to allowance, and the claim set discussed below is the set as filed and published. Inventors are listed as Yang Lu, Donald Morgan and QiaoHua Dong.

Read the independent claim rather than the title. Claim 1 recites a method performed by a memory device comprising three steps: receiving a refresh command; concurrently refreshing, during a time interval and based on that command, at least two rows within a bank, those rows being associated with different refresh sections of the bank; and then the limitation that carries the weight of the claim.

performing at least two update procedures in a serialized manner during the time interval to update usage-based-disturbance data stored within the at least two rows— Performing Serialized Update Procedures during a Refresh Period, US20260204307A1

Two things in that limitation do the work. The first is the tension between concurrently and in a serialized manner: the rows are refreshed at the same time, but the bookkeeping attached to those rows is not updated at the same time. The second is the temporal container — the serialized updates happen during the time interval, the same interval in which the concurrent refresh occurs. A device that refreshed multiple rows together and then updated their counters afterward, outside that interval, would fall outside the recited scope. "Usage-based disturbance" is the document's own term throughout; it is the vocabulary a memory designer would recognize as covering the read-disturb class of failure that the wider industry discusses under the Rowhammer label, though that word does not appear in this filing.

What the dependents narrow

Claim 2, the first dependent, supplies the concrete data type: "The method of claim 1, wherein the usage-based-disturbance data comprises activation counts associated with the at least two rows." That places the claimed subject matter squarely in per-row activation counting rather than any broader notion of usage telemetry. Claims 3 and 4 go to what an update does — setting those counts to at least one default value, with claim 4 specifying that the default may be a same fixed value, different randomized values, or values calculated from current values of the activation counts. Randomized reset values are a notable option to see recited alongside a fixed reset.

Claim 5 introduces the structural reason serialization appears in claim 1 at all: the at least two rows are associated with different column segments, and those different column segments are associated with different column repair solutions. Claim 6 continues that thread, tying the update procedures to activating different sets of column select lines associated with those repair solutions; the published text of claim 6 uses the unhyphenated form "usage-based disturbance data," a departure from the hyphenated form used elsewhere in the document, and this brief does not quote it. Claim 7 then decomposes the interval into a first portion and a second portion, with the second occurring after the first — the explicit ordering that "serialized" implies. Claim 8 extends the arrangement to a third row and third refresh section. Claim 9 caps the sequence with the timing bound: all three update procedures are performed prior to an end of a refresh cycle time (tRFC) corresponding to the refresh command.

That tRFC bound is the commercial hinge of the disclosure. A DRAM device does not get extra time to do disturbance bookkeeping; it gets whatever fits inside the refresh window the JEDEC timing budget already allocates. The application's approach, as described, is to fit the serialized updates inside that existing window rather than to ask for a new one.

Claim 10, claim 17, and the classification

Claim 10 is the apparatus counterpart. It recites a memory device with at least one bank whose multiple rows are associated with different refresh sections and each of which is configured to store usage-based-disturbance data corresponding to the row, plus two distinct structural elements: circuitry coupled to the bank and configured to concurrently refresh at least two rows, and a separate circuit coupled to the bank and configured to perform the at least two serialized update procedures. Splitting refresh circuitry from update circuitry is a deliberate apparatus-side distinction, and its dependents track the method chain closely — claims 12 through 14 walk column segments, column repair solutions and column select line activation across first, second and third rows; claim 16 adds a row column delay before the first update procedure begins.

Claim 17 is the third independent claim and approaches the same operation from the other end. Rather than reciting a refresh step, it recites performing a first update procedure during a first portion of a time interval on data stored within a first refreshed row, and a second update procedure during a second portion on a second refreshed row, each row associated with its own refresh section and column segment. The refresh is presupposed by the word "refreshed" rather than positively recited, which makes claim 17 a narrower-looking but differently anchored path to similar subject matter. Its dependents 19 and 20 map to activation counts and to column select line activation per repair solution respectively.

The publication carries CPC codes G11C 11/40618, G11C 11/40603 and G11C 11/40615 — all within the G11C 11/406 group covering refresh operations in dynamic memory, with the 40618 subgroup reaching refresh-related row-access counting. That is the shelf where disturbance-mitigation work has been accumulating across the DRAM suppliers, and this application sits in it rather than in a security or error-correction class, which is itself informative about how the subject matter is framed.

The filing does not stand alone in the assignee's recent publication flow. US20260204308A1 published the same day on outputting data from a memory device. Nearby publications include US20260196285A1 on storing error information and providing recommendations based on same, US20260188417A1 on forcing memory cell failures in a memory device, and US20260186896A1 on storing memory metadata — three filings that, like this one, concern data the device keeps about itself. Process-side publications such as US20260198284A1 on conductive interconnects round out the cluster. Readers tracking this area should note the status distinction: every record cited here is a published application. Scope is not fixed until prosecution closes.