SRAM bit-cell area is the number foundries cite to prove a new logic node actually shrank, because SRAM scales worse than logic and every fractional gain is hard-won. At Taiwan Semiconductor Manufacturing Co., Ltd., a striking amount of that bit-cell IP carries a single inventor name: Jhon Jhy Liaw. A 2022 portfolio sweep shows how one name anchors the foundry's SRAM cell strategy.

Take the fin-pitch slice. US11437385B2, "FinFET SRAM cells with reduced fin pitch" (issued 2022-09-06, CPC H01L 27/1104 and G11C 11/412), claims a cell layout that packs fins more tightly - directly attacking cell area. Reduced fin pitch is one of the few levers left for SRAM scaling once transistor count per cell is fixed at six.

“A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second d…”— U.S. Patent No. 11,437,385 source

Then the fin-topology slice. US11488966B2, "FinFET SRAM having discontinuous PMOS fin lines" (issued 2022-11-01), claims a cell where the PMOS fins are deliberately broken into discontinuous segments - a layout trick that relaxes patterning constraints and shrinks the cell. The discontinuity is the claimed limitation.

And the array slice. US11410719B2, "SRAM array" (issued 2022-08-09, CPC G11C 11/412 and H01L 27/1104), and US11342337B2, "Structure and method for FinFET SRAM" (issued 2022-05-24), extend from the single cell up to the array organization. Together they show Liaw's portfolio covering the cell and how cells assemble.

The facet data for SRAM-cell-fin queries in 2022 shows TSMC's various name-spellings collectively leading the class, with Liaw recurring across the grants. This concentration is unusual and strategically deliberate: SRAM cell design is a specialized art, and TSMC has kept it under a master practitioner whose name on a patent is itself a competitive signal.

For a competitive-intelligence analyst, the lesson is to track inventors, not just assignees. Liaw's grant cadence is a proxy for where TSMC's SRAM scaling effort is pointed - fin pitch, fin topology, then the move to GAA-based SRAM that shows up in his and others' later filings. The white space he leaves - exotic non-6T cells, gain-cell SRAM - is where competitors and research labs concentrate instead.