Chiplets only pay off if the links between them are cheap in power and area. Most die-to-die interconnects rely on a physical-layer (PHY) circuit to drive and receive signals — and that PHY is a meaningful energy and silicon cost. Intel Corporation's late-2024 grant claims doing without it: a PHY-less die-to-die I/O.

US12159840B2, "Scalable and interoperable PHYLESS die-to-die IO solution" (issued 2024-12-03), is classified in H01L 23/5386 (internal connections) with H01L 23/5381 and H01L 24/16 (bumps). The claim's defining limitation is in the title: a die-to-die I/O that is PHY-less, plus the requirement that it be scalable and interoperable.

“Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate.”— U.S. Patent No. 12,159,840 source

Construe what PHY-less requires. Independent claim 1 recites a first die with a first IO bump map at a first pitch and a second die with a second IO bump map at a different second pitch, interconnects between the two bump maps, and a bridge die embedded in the substrate carrying those interconnects. The bridge die has a first metal layer above a second metal layer, and the routing crisscrosses: the first metal layer couples an outermost interconnect of the first die to a second-outermost interconnect of the second die, while the second metal layer couples an outermost interconnect of the second die to a second-outermost interconnect of the first die. That deliberate two-layer crossover is how two dies with mismatched bump pitches are made to line up signal-for-signal without a PHY's serializer/aligner doing the work electrically.

The numbers in the dependents are what make the PHY-less story concrete. Claim 5 sets the first pitch at roughly 55 µm or larger and the second at roughly 55 µm or smaller; claim 6 lists the fine-side pitch at about 45, 36, or 25 µm. Claim 7 requires the two bump maps to have an equal number of signal bumps — claim 8 fixes that count at sixty — so the link is a fixed-width parallel bus rather than a serialized one, which is precisely what lets the PHY be dropped. Claim 2 matches the bump-map widths along the die edges, and claim 9 splits each bump map into transmitter and receiver regions along the edge. Claim 10 details a five-metal-layer substrate with alternating power/ground and signaling layers, transmitter-to-receiver coupling on the second and fourth layers, and claim 11 depopulates power and ground pads under the transmitter region to make room for the dense parallel signaling.

The receiver-side physics is claimed too. Claim 17—20 describe a die whose transmitter bumps sit directly over their transmitter circuits, while the receiver bumps are offset from their circuits and reached by a horizontal "leadway" segment in the metal — claim 19 puts that leadway at roughly 200 µm or greater, and claim 20 quantifies the penalty it adds at about 65 ohms in the channel. Spelling out the parasitic resistance of the routing detour is exactly the kind of disclosure that supports a link designed to work without a heavy PHY restoring the signal; the design is tolerant because the connection is short and dense, per the bridge-die geometry.

The "interoperable" element ties to UCIe (Universal Chiplet Interconnect Express), the standard Intel championed for cross-vendor chiplet connection. A PHY-less, interoperable, fixed-sixty-signal I/O over an embedded bridge is aimed at the UCIe-era vision of mixing chiplets from different makers efficiently. The design-around space is the I/O architecture: a competitor using a conventional PHY-based die-to-die link, a serialized rather than fixed-width parallel bus, or a single-metal-layer bridge without the crossover, reaches chiplet interconnect outside a claim that turns on the two-layer crossover bridge, the equal-signal-bump parallel scheme, and the offset-receiver leadway.

It is worth separating the several independent claims, because they fence different things. Claim 1 and the parallel system claim 22 require the full two-metal-layer crossover bridge die. Claim 10 drops the bridge framing and instead claims a five-metal-layer package substrate — first, third, and fifth layers as power/ground, second and fourth as signaling — with the first die's transmitter region coupled to the second die's receiver region through channels in the second metal layer and the reverse direction through the fourth, the two channel sets made equal in length (claim 16). Claims 11—13 then depopulate power and ground pads from the second signaling layer under the transmitter region (all of them, per claim 12) while leaving the fourth layer's pads intact, freeing routing space exactly where the dense transmit channels need it. Claim 17's die-level claim captures the receiver-offset trick independently: transmitter bumps aligned over their circuits, receiver bumps deliberately not aligned and reached by a long horizontal leadway. Taken together the claims describe a fixed-width, source-synchronous-style parallel link whose signal integrity comes from short, length-matched, layer-segregated routing over an embedded bridge rather than from an equalizing PHY — which is the whole point of calling it PHY-less, and which is why the quantified parasitics (claim 20's ~65 ohms, claim 19's ~200 µm leadway) appear in the claims at all.

For competitive intelligence, this grant sits in Intel's deep die-to-die portfolio and signals Intel pushing chiplet I/O toward maximum efficiency. As UCIe adoption grows, PHY-less and low-PHY interconnect claims — with the specific bridge and bump-map geometry claimed here — become strategically important to map for anyone building standardized chiplet I/O.