Chiplets only pay off if the links between them are cheap in power and area. Most die-to-die interconnects rely on a physical-layer (PHY) circuit to drive and receive signals - and that PHY is a meaningful energy and silicon cost. Intel Corporation's late-2024 grant claims doing without it: a PHY-less die-to-die I/O.
US12159840B2, "Scalable and interoperable PHYLESS die-to-die IO solution" (issued 2024-12-03), is classified in H01L 23/5386 (internal connections) with H01L 23/5381 and H01L 24/16 (bumps). The claim's defining limitation is in the title: a die-to-die I/O that is PHY-less, plus the requirement that it be scalable and interoperable.
Construe what PHY-less requires. Eliminating the PHY means relying on the extremely short, dense connection that advanced packaging provides - when two dies are bonded or bridged at micron pitch, the signal integrity can be good enough to skip the heavy PHY drivers a long link needs. The claim turns on the specific I/O scheme that exploits that to drop the PHY.
The 'interoperable' element ties to UCIe (Universal Chiplet Interconnect Express), the standard Intel championed for cross-vendor chiplet connection. A PHY-less, interoperable I/O is aimed at the UCIe-era vision of mixing chiplets from different makers efficiently. The claim defends Intel's approach to that.
The design-around space is the I/O architecture. A competitor using a conventional PHY-based die-to-die link (standard UCIe PHY), or a different low-power I/O, reaches chiplet interconnect outside a claim requiring the PHY-less scheme. The value is precisely the energy saved by removing the PHY.
For competitive intelligence, this grant sits in Intel's deep die-to-die portfolio and signals Intel pushing chiplet I/O toward maximum efficiency. As UCIe adoption grows, PHY-less and low-PHY interconnect claims become strategically important, and Intel's early position here is one to map for anyone building standardized chiplet I/O.