What does a high-bandwidth memory (HBM) patent claim, and how is the stack classified? HBM is a memory architecture that achieves its bandwidth by going vertical: several dynamic-random-access-memory (DRAM) dies — the "core" dies — are stacked on top of a "base" die and connected through the silicon by through-silicon vias (TSVs), short vertical interconnects that pass straight through each die. Because data travels through the stack rather than around its perimeter, the interface can be enormously wide, which is the source of HBM's bandwidth advantage over conventional planar memory. The base die at the bottom carries the logic that interfaces the stack to the host processor. The patents claim that arrangement and the interface logic on the base die. In the Cooperative Patent Classification (CPC) scheme, the stacked-die structure is classified at H01L 25/0657, which the USPTO titles "Stacked arrangements of devices." That class is where 3D-stacked memory grants are found.

A very recent grant shows where HBM claims are moving. Samsung Electronics Co., Ltd. holds US Patent 12,664,087 (issued June 23, 2026), titled "Memory device, CXL memory device, system in package, and system on chip including high bandwidth memory." Its independent claim 1 recites:

A compute express link (CXL) memory device comprising: a high bandwidth memory (HBM) comprising a CXL base die and a plurality of core dies that are sequentially stacked on the CXL base die, wherein the CXL base die comprises an HBM controller; a CXL interface circuit; a bus configured to connect the HBM controller to the CXL interface circuit... and an HBM interface intellectual property (IP) core configured to convert data transmission and reception with dynamic random access memory (DRAM) of the plurality of core dies...— US 12,664,087 B2, claim 1, source

The limitations show what the patent adds on top of the basic HBM stack. First, the foundational HBM structure: "a CXL base die and a plurality of core dies that are sequentially stacked on the CXL base die." That is the core-on-base stack. Second, the base die "comprises an HBM controller" and "a CXL interface circuit" — the patent moves the memory controller and a Compute Express Link interface onto the base die itself. Third, an "HBM interface intellectual property (IP) core configured to convert data transmission and reception" between the host protocol and the DRAM. The claim therefore is not a bare "stack DRAM on a base die" recitation; it is a specific base-die architecture that integrates CXL connectivity and a protocol-converting IP core. Dependent claim 5 supplies the interconnect: "the CXL base die and the plurality of core dies of the HBM are stacked through a through silicon via (TSV) to form a three-dimensional (3D) memory stack," confirming the TSV-based 3D structure that defines HBM.

What the dependents reveal about direction

The dependents point to where the architecture is heading. Claim 1 itself recites that the HBM interface IP core "operates regardless of a Joint Electron Device Engineering Council (JEDEC) standard" — explicitly a non-JEDEC, custom interface, a notable limitation given that mainstream HBM has been defined by JEDEC standards. Claim 2 breaks the IP core into a "through silicon via (TSV) input and output (IO) block" and a "soft macro block" that performs protocol conversion. Claim 3 recites that the CXL interface supports "peripheral component interconnect express (PCIe) and universal chipset interconnect express (UCIe)" — tying the memory stack to the die-to-die interconnect standards used in chiplet systems. Claim 4 connects the device to "an application specific integrated circuit (ASIC) die via an interposer" carrying "at least one central processing unit (CPU), at least one graphics processing unit (GPU), and at least one neural processing unit (NPU)." Read together, the dependents describe HBM being repositioned as a CXL- and UCIe-connected memory tier for AI accelerators, not just a JEDEC-standard bandwidth part. For a portfolio analyst, that is the strategic signal in the claim set.

How the class organizes stacked memory

For mapping the HBM landscape, H01L 25/0657, "Stacked arrangements of devices," is the structural anchor for the physical stack, and related grants in this area also carry H01L 25/18 and H01L 25/50 for the assembled package and its manufacture. The CPC note records that H01L 25/0657 has been impacted by reclassification into newer H10B and H10x subgroups, so a complete search reads both the legacy class and its successors. The Samsung CXL patent, notably, is classified at G06F 12/0246 — a memory-management code — reflecting that its claimed contribution is as much about the interface and controller logic on the base die as about the physical stack. That dual character is the point: an HBM patent can be a stacking-structure claim, a package claim, or, increasingly, a controller-and-interface claim, and the classification spread tells a reader which kind it is.

What the record shows is that HBM, at the claim level, is a core-on-base TSV stack whose patentable frontier has moved into the base die. US 12,664,087 claim 1 recites DRAM core dies sequentially stacked on a CXL base die that carries an HBM controller, a CXL interface, and a protocol-converting IP core, with claim 5 specifying the TSV-based 3D stack — and the dependents tie the part to PCIe, UCIe, and AI-accelerator integration while operating outside the JEDEC standard. CPC H01L 25/0657 classifies the stacked-device arrangement. The basic idea of stacking DRAM is not what this claim protects; the specific CXL-enabled base-die architecture is. How far any such claim reaches against a competing memory stack depends on that claim's exact limitations and its prosecution history.