US11664374B2, "Backside interconnect structures for semiconductor devices and methods of forming the same" (issued 2023-05-30), is classified in H01L 27/0886 (FET integrated circuits) with H01L 23/50 (interconnect arrangements), H01L 29/41791, and H01L 29/66795. The claim covers the backside interconnect structure - the routed metallization on the wafer back - and the method that forms it and ties it to the front-side device.
Construe the progression from the 2021 rail claim. A single backside power rail is one wire; a backside interconnect structure is a routed network with vias and multiple levels. The 2023 claim fences the more complex arrangement, and its limitations specify how that backside network connects through to the active devices on the front.
The connection limitation is the crux. Backside metal is useless unless it reaches the transistors, so the claim turns on the via or contact scheme that bridges back-side interconnect to front-side source/drain or rail. That bridging structure is the element a competitor must design around.
TSMC's filing cadence here - 2021 rail, 2023 interconnect, then 2023 packaged-device backside-rail grants - is a textbook family build-out: stake the foundational concept early, then fence each elaboration as the technology matures toward volume. The priority dates compound into a defensible position on backside power.
For an IP strategist, the 2023 grant is the marker that BSPDN had moved from research to near-production at TSMC. Anyone shipping backside power at 2nm - Intel's PowerVia, Samsung's BSPDN - operates in a thicket where TSMC's 2021-2023 family is a major presence, and freedom-to-operate requires reading the connection-scheme claims closely.