It is tempting to think EUV lithography IP is an ASML monopoly. ASML does hold the scanner — the light source, the optics, the stage. But the process built around that scanner is a different patent landscape, and it is anything but locked up. The June 2026 record shows foundries and process-tool makers claiming the recipe steps that turn an EUV exposure into a usable pattern. For claim-construction purposes, that distinction — hardware versus process — is everything.
Take Taiwan Semiconductor Manufacturing Company, Ltd.'s US12653001B2, "Method of manufacturing semiconductor devices and pattern formation method" (issued 2026-06-09). Its classifications are tightly G03F 7/70033 and G03F 7/70 (lithographic process / exposure apparatus interaction) plus H01L 21/0275 (pattern formation). Construe this as a method claim: the protected scope is a sequence of steps, and the question for any reader is which steps the independent claim recites as essential. A pattern-formation method patent is dangerous precisely because a competitor running EUV in a fab is performing steps; if the claimed sequence matches the fab flow, infringement is hard to design around without re-architecting the recipe.
TSMC's US12645150B2, "Lithography system and methods" (issued 2026-06-02; CPC G03F 7/70316, 7/70033), claims at the system level — apparatus plus method. The construction caution here is the inverse of a method claim: a "system" claim with many recited components is often narrower than it sounds, because every recited component is a limitation that must be present to infringe. The broad title ("lithography system") does not broaden the claim; the element list does the limiting.
Applied Materials, Inc. claims a single process step in US12645157B2, "Vacuum bake for EUV lithography" (2026-06-02; CPC G03F 7/70875, 7/40). This is the most surgically narrow of the three, and arguably the most valuable per its scope: a vacuum bake of EUV resist is a specific, checkable step. If your resist flow includes a vacuum bake under the recited conditions, you are squarely inside; if you anneal at atmosphere or skip the step, you are outside. Narrow claims like this are easy to construe and easy to either infringe or avoid — there is little ambiguity to litigate.
Walking the three as limitations rather than topics: TSMC's pattern-formation method protects a recipe sequence (design-around = change the sequence), its system patent protects a specific apparatus configuration (design-around = omit a recited component), and Applied Materials' vacuum bake protects one step under specified conditions (design-around = change the bake environment). None of them touches ASML's scanner — and ASML's patents, conversely, do not reach these process recipes.
The construction lesson for an EUV freedom-to-operate review: do not stop at "we bought an ASML scanner, so we have rights." The scanner license does not clear the resist chemistry, the bake steps, or the pattern-formation method — those are separately claimed by separate assignees, and the June 2026 grants show the foundries and tool makers fencing them step by step.