What does Intel's cavity-less glass-core interconnect grant actually claim? The independent claim of US12672562B2 ("Cavity-less interconnect component on glass core," issued June 30, 2026, assigned to Intel Corporation) recites a glass layer threaded by conductive-filled through-glass vias, a local interconnect component attached to the glass layer's upper surface — not embedded in a cavity — a mold layer whose top is co-planar with that component, a conductive pillar over a second via, and two dies bridged across the component. The threshold fact belongs up front: this is an issued grant, a B2, granted in the June 30, 2026 drop — the recited scope is what has issued, not a pending application's reach.

Walk claim 1 element by element, because the word "cavity-less" is doing the distinguishing work. There is a glass layer with an upper surface, a lower surface, and a plurality of through-glass vias (TGVs) traversing top to bottom, substantially filled with conductive material. A local interconnect component is attached to the upper surface of the glass layer — sitting on it, positioned over a first TGV — and carries a first and a second conductive contact on its upper surface that are in electrical communication. A mold layer lies on the glass around the component, with its upper surface co-planar with the component's upper surface. A conductive pillar stands over a second TGV, extending from the glass surface up to the mold surface and exposed there. Then a first die attaches to the first conductive contact and the pillar, and a second die attaches to the second conductive contact. The two dies are bridged through the component while also reaching the substrate below through the TGVs and pillar.

An apparatus, comprising: a glass layer having an upper surface, a lower surface, and a plurality of through-glass vias (TGVs) … a local interconnect component attached to the upper surface of the glass layer … a mold layer located on the upper surface of the glass layer and adjacent to the local interconnect component, the mold layer having an upper surface co-planar with the upper surface of the local interconnect component … a first die attached to the first conductive contact and the conductive pillar; and a second die attached to the second conductive contact.— Cavity-less interconnect component on glass core, US12672562B2

The dependent claims narrow what the component and its surroundings are. Claim 4 recites the local interconnect component as a silicon bridge; claim 5 recites a through-silicon via in that bridge connecting to a third TGV so the first die reaches the substrate through the bridge. Claim 6 recites a package substrate attached to the TGVs at the lower glass surface; claims 7 and 8 recite redistribution layers above the mold and below the glass. Two further independent claims re-recite the apparatus by attachment method: claim 12 attaches the interconnect component to a first TGV by hybrid bonding, and claim 18 attaches it via a bond film. Claim 24 recites the method — pattern and fill the TGVs, form a copper pillar, attach the component, overlay with mold, planarize to expose the pillar and contacts, then attach the two dies. Scope here is built from those attachment-and-planarization limitations, not from the bare notion of a bridge on glass.

Where it lands in the CPC landscape

The classification puts this squarely in the reorganized advanced-packaging space rather than in device fabrication: US12672562B2 carries CPC symbols across the H10W assembly-and-packaging subclasses (for example H10W 70/65 and H10W 90/00), the neighborhood for die-to-die interconnect and package assembly. The deliberate distinction the claims draw is against the cavity-embedded route in the companion grant US12672564B2 ("Technologies for vertically interconnected glass core architecture"), whose claim 1 instead recites a bridge die disposed in a cavity that extends the full thickness of the glass layer with dies bonded above and below. One drop, two independent claim sets, two physical routes to the same die-to-die bridging problem — one buries the bridge in the glass, the other sets it on top and surrounds it with planarized mold.

The companion records in the same June 30 window classify into adjacent corners of the glass-packaging map, which makes this a cluster read. US12672239B2 ("Hybrid bonded passive integrated devices on glass core") claims hybrid bonds between contact pads of a glass core layer and the pads of discrete passive components, with through-glass vias extending through only the glass core. US12672559B2 ("Low insertion loss coaxial through-hole for highspeed input-ouput") is directed to a coaxial through-hole in a core layer — a first through-via surrounded by a grounded conductive layer, electrically isolated from it. And US12672566B2 ("Wireless chip-to-chip high-speed data transport") is directed to microbump-antenna wireless die-to-die transmission. Read together, the claims describe Intel working the glass-substrate interconnect problem across embedded bridges, on-glass bridges, on-glass passives, coaxial vias, and wireless links.

What the record shows, and what it does not

Intel Corporation is the named assignee on each record, all issued June 30, 2026 as version B2 grants. US12672562B2 is directed to a cavity-less interconnect component attached to the upper surface of a TGV-threaded glass layer, surrounded by co-planar mold, with a conductive pillar over a second via and two dies bridged across the component — with silicon-bridge, hybrid-bonding, bond-film, and method variants in the dependent and further independent claims. Because these are issued grants rather than applications, the recited limitations define coverage that has issued; the coaxial-via, on-glass-passive, and embedded-bridge companions define their own separately claimed structures. Nothing in the record speaks to which products, if any, practice these claims, or to enforceability or scope beyond the language the claims recite.