On June 16, 2026 the U.S. Patent and Trademark Office issued U.S. Patent No. 12,660,599 B2 to International Business Machines Corporation, titled "Hybrid signal and power track for stacked transistors." The grant is not a new transistor; it is a wiring architecture. It addresses the question that dominates the transition to complementary FET (CFET) stacks, where one device sits directly atop another: once you put two transistors in the same vertical column, how do you get signal and power to both of them without the routing collapsing into a congested mess on a single metal level?
The named inventors are Tao Li, Kisik Choi, Albert M. Young, Julien Frougier, and Ruilong Xie. The classification places the grant squarely in the wafer-level system-and-power-rail space, with CPC symbols including H10W 20/427, H10W 20/20, and H10W 90/297 — codes that describe power-rail and interconnect arrangements rather than channel materials or gate stacks. That is the first signal of what this patent is: an interconnect grant, read it as wiring, not as a device-physics breakthrough.
"The semiconductor device comprises a first transistor stacked above a second transistor."— U.S. Patent No. 12660599, source
The core arrangement described in the abstract is a division of labor across the two faces of the wafer. A frontside power rail is electrically coupled to a source/drain epitaxy of the first (upper) transistor. A backside power rail is electrically coupled to a source/drain epitaxy of the second (lower) transistor. So far this mirrors the conventional logic of backside power delivery: pull the power network off the crowded front side and route it from beneath the device. What makes this grant distinct is the third element — the signal routing.
The element that matters: a frontside signal line reaching the bottom device
The abstract specifies a plurality of frontside signal lines, and within them a first frontside signal line that is electrically coupled to a source/drain epitaxy of the second transistor — the bottom one. Crucially, that frontside signal line does not reach the bottom transistor by the obvious path. The record states the frontside signal line is connected to the source/drain epitaxy "through a backside contact and an interlevel via." In plain terms: a signal that lives on the front-side metal must dive down, cross to the backside contact landing on the lower device, and come back up through an interlevel via to make the connection. The patent is claiming the hybrid path itself — the deliberate mixing of front-side signal routing with back-side contact structures to service a buried transistor.
That is the limitation a competitive-intelligence read should anchor on. A pure backside-power scheme keeps signal on the front and power on the back, a clean partition. IBM's described device breaks the partition on purpose: power is split across both faces (frontside for the top device, backside for the bottom device), and at least one signal line is allowed to traverse the backside contact stack to reach the lower transistor. The interlevel via is the connective tissue that makes the hybrid track legal as a circuit. Anyone evaluating design-around space has to look at whether the bottom device's signal can be reached without routing through a backside contact and an interlevel via — because that specific combination is what the abstract foregrounds.
Why this lands in the CFET conversation
Stacked transistors are the structural premise of CFET, the architecture the leading-edge foundries and IDMs are positioning beyond gate-all-around nanosheets. The appeal of stacking an nFET over a pFET (or vice versa) is area: two devices in one footprint. The cost is routing. Every stacked pair doubles the number of source/drain terminals that need contact in the same vertical column, and the front-side metal stack was already the bottleneck before anyone added a second transistor underneath. Backside power delivery is the industry's answer to half of that problem — move the power network to the back. IBM's grant addresses the other half: what to do when even with backside power, the lower transistor's terminals are hard to reach from the front without congesting the very levels you were trying to relieve.
The answer described here is to treat front and back as a single routing fabric rather than two segregated planes. Power is assigned per device to whichever face is closer or less congested. Signal is allowed to cross faces through backside contacts and interlevel vias when that shortens or de-congests the path. The grant is, in effect, a claim on a routing discipline for the CFET era — a recognition that the front/back split is a design knob, not a fixed wall.
A note on scope discipline, in keeping with how chipclaims reads grants: the language summarized here is from the abstract, which describes the embodiment, not the metes and bounds of the independent claim. The abstract tells you what the invention is centered on — frontside power to the top device, backside power to the bottom device, and a frontside signal line reaching the bottom device through a backside contact and an interlevel via. The enforceable scope lives in the independent claim and its dependents, which will specify exactly which structures are required and which are optional. What the record makes clear is the direction of IBM's interconnect strategy for stacked logic: hybrid, cross-face routing built around backside contacts. For competitors mapping the CFET wiring thicket, US 12,660,599 is a marker of where one of the most prolific logic-IP holders has planted a flag.