In a conventional 2.5D package, dies attach to the interposer through microbumps — tiny solder balls that limit how fine the connection pitch can go. Eliminating them by bonding the interposer directly to the die pads pushes density further and improves signal integrity. Taiwan Semiconductor Manufacturing Co., Ltd.'s late-2024 grant claims that direct-bonded interposer.

US12165952B2, "Interposer directly bonded to bonding pads on a plurality of dies" (issued 2024-12-10), is classified in H01L 23/4334 (cooling/heat-spreading) with H01L 21/4857/486 (substrate/interposer fabrication), H01L 24/08/32/73/83 (bonding), and H01L 25/0655. The claim is on an interposer directly bonded — not microbumped — to the bonding pads of multiple dies.

“A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate.”— U.S. Patent No. 12,165,952 source

Construe the direct-bond limitation. Independent claim 1 recites a first semiconductor substrate, a plurality of first dies bonded to it, a plurality of thermal conductive patterns also bonded to it, and an interposer — itself a second semiconductor substrate with through-vias — bonded to the first dies, with the dies and thermal patterns sandwiched between the substrate and the interposer. The novelty is the absence of an intervening microbump array: the interposer's surface bonds straight to the die pads, hybrid-bonding-style. Claim 7 makes the bond explicit — the dies carry second bonding pads in a second bonding layer that bonds directly to the interposer's first bonding layer, pad-to-pad. Claim 9 frames the same interface from the other direction, with the second die's bonding pads "directly bonded" to the first dies' bonding pads.

The thermal conductive patterns are not incidental — they are a recited element and the reason for the cooling-oriented CPC code. Sitting alongside the active dies and bonded to both the carrier substrate and (per the method) the interposer, they form dummy thermal paths that carry heat out of a bumpless, encapsulated stack where there is no solder layer and little air gap to conduct through. Claim 2 adds an encapsulant around the dies and thermal patterns, and claim 3 has its surface coplanar with the dies and patterns, so the whole assembly presents a flat face for the direct bond. Claims 4—6 detail the interposer's internals: a first redistribution layer between its silicon and the dies, a bonding structure of pads in a bonding layer, a second RDL and conductive terminals on the far side, and through-vias connecting the two RDLs — the vertical path that carries signal up through the bonded interposer to the package balls.

The method claims (16—20) describe the build: adhere the first dies to a carrier, form thermal patterns beside them, bond an interposer onto the dies through one surface so its bonding pads meet the die pads and its thermal patterns meet the die-side thermal patterns (claim 19, "directly bonded"), then form terminals on the opposite surface and dice. This extends hybrid bonding from the die-to-die context into the die-to-interposer interface: where earlier TSMC bonding patents fenced stacking two dies, this one fences bonding several dies onto a shared interposer without bumps, with integral thermal patterns — a denser, more electrically capable, and better-cooled version of CoWoS.

The second product independent claim, claim 9, recasts the same interface in face-to-face terms and is worth construing on its own. It recites a carrier holding a plurality of first dies in a first dielectric layer, adhered to the carrier by an adhesion layer, the dies carrying first bonding pads; first through-vias in that dielectric; and a second die whose second bonding pads are "directly bonded to the first bonding pads," with first redistribution patterns between those pads and the second die's through-vias. Claim 13 adds that the first dies' bonding layer surrounds their pads and the second die's bonding layer is directly bonded to it — the hallmark dielectric-to-dielectric plus metal-to-metal hybrid bond. Claim 12 notes the second die carries active devices, so the "interposer" here can itself be an active die, blurring the line between interposer and top tier. Several dependents pin down edge geometry that signals a diced-from-reconstituted-wafer process: claim 10 has the carrier sidewall flush with the adhesion layer, claim 11 has it flush with the dielectric and the second die, and claim 15 has the first through-vias in direct contact with the carrier. Read with the method's final dicing step (claim 20), the family describes wafer-level reconstitution of known-good dies followed by a bumpless interposer bond and singulation — a manufacturable route to the structure, not just the static cross-section.

The design-around space is the attach method. A competitor using microbump attach (conventional CoWoS-S), or bonding through an intermediate solder or adhesive layer rather than pad-to-pad, reaches multi-die-on-interposer integration outside a claim requiring direct interposer-to-pad bonding plus the co-bonded thermal patterns. As bumpless attach spreads, the claim's relevance grows.

The CPC mix is telling about what TSMC chose to emphasize. The lead code H01L 23/4334 sits in cooling and heat-spreading — the thermal conductive patterns — rather than purely in the bonding or stacking codes, which is unusual for a packaging claim and signals that the co-bonded thermal paths are treated as a core feature, not an afterthought. The bonding codes H01L 24/08/32/73/83 cover the direct pad-to-pad and dielectric-to-dielectric interfaces, H01L 25/0655 the stacked-device assembly, and H01L 21/4857/486 the interposer fabrication. A freedom-to-operate read therefore has to weigh two limitations together: the bumpless direct bond and the integral thermal patterns co-bonded across the same interface. Dropping either — microbumps instead of direct bond, or no dedicated thermal patterns — moves a design off the literal claims even if the rest of the CoWoS-style stack looks similar.

For a portfolio analyst, this 2024 grant shows TSMC pushing CoWoS toward bumpless, higher-density integration with built-in thermal management — the natural endpoint of the advanced-packaging arms race. It sits within TSMC's enormous and growing 3D-packaging family, and anyone building a high-density multi-die package on an interposer should read TSMC's direct-bond claims as part of the freedom-to-operate map.