What does an asymmetric-CMOS application actually claim, past the phrase "hybrid CMOS architecture" in its title? The hero record this week, Intel (INTC) application US20260190475A1 ("Asymmetric Stacks of NMOS and PMOS Transistors in a Hybrid CMOS Architecture," published July 2, 2026), turns on a geometric limitation rather than a material one. Independent claim 1 recites a first transistor and a second transistor on a base layer, each with channel regions wrapped by a gate, where — and this is the limitation doing the work — the first channel regions are in first planes that are axially spaced from the second planes holding the second channel regions. In plainer terms, the two devices' channel stacks are not coplanar; one sits vertically offset from the other. Note the threshold point first: this is a published application, not a granted patent. It defines the scope Intel is pursuing, not scope an examiner has allowed.

Walk claim 1 element by element and the structure is spare. There is a base layer; a first transistor with a stack of channel regions, a wrapping gate region, and source/drain regions at the ends; a second transistor built the same way; and the requirement that the two stacks occupy axially spaced planes. Everything that makes the pair "hybrid" lives in the dependent claims. Claim 5 recites that the first channel is silicon and the second is one of germanium, silicon-germanium, or germanium-tin. Claim 6 recites a p-type work-function metal on one gate and an n-type on the other. Claims 3 and 4 reach the case where the two stacks hold an unequal number of channel regions and have unequal heights. The independent claim, in other words, is written around the vertical offset; the material pairing and the sheet-count mismatch are narrowing limitations layered on top.

An integrated circuit device comprising: a substrate comprising silicon; a first gate-all-around (GAA) transistor on the substrate, wherein the first GAA transistor includes a first plurality of channel regions in a first stack; and a second GAA transistor on the substrate, wherein the second GAA transistor includes a second plurality of channel regions in a second stack, wherein the first plurality of channel regions of the first GAA transistor are not coplanar with the second plurality of channel regions of the second GAA transistor.— ASYMMETRIC STACKS OF NMOS AND PMOS TRANSISTORS IN A HYBRID CMOS ARCHITECTURE, US20260190475A1

The application carries more than one independent claim, and reading them together shows how the scope is framed. Claim 8, quoted above, restates the invention as an integrated circuit device and names the transistors explicitly as gate-all-around (GAA) devices on a silicon substrate, again pinned to the non-coplanar limitation. Claim 16 casts it as a method: forming a first set of channels of one semiconductor material and a second set of another material such that the two are "asymmetrically aligned on opposite sides of a space defined therebetween," with subsequent claims describing growing an interleaved stack of the two materials and selectively removing portions to leave each device its own channel material. Apparatus and method are claimed in parallel — a structure and a way to build it — which is common in device filings and tells an IP reader that the applicant is reaching for both the article and its fabrication.

Where it lands in the CPC landscape

The classification places the application in the reorganized device space. US20260190475A1 carries CPC symbols including H10D 84/856 and H10D 84/851 — the CMOS-integration corner of the H10D group that now houses what the former H01L subclasses covered for semiconductor devices — along with device-level symbols such as H10D 62/121 and H10D 30/0191. The presence of the H10D 84/8xx integration symbols, rather than only single-device subclasses, is the signal that the application is directed at how two transistors are built together on one substrate, which is exactly what an asymmetric-CMOS claim is about. For readers still mapping the old codes, this is the neighborhood of transistor-integration IP that gate-all-around logic is filed into.

The companion Intel records in the same publication window classify into the adjacent backside-processing corner of the same map, which is what makes this a cluster rather than a one-off. US20260190418A1 ("Backside Contacts for Improved Source/Drain Connection") claims, in its independent claim, a backside conductive contact that extends through a dielectric layer and into part of the source/drain region, with a dielectric liner on its sidewalls contacting the bottom surface of that region — a limitation about where the liner sits relative to the source/drain. US20260190424A1 ("Self-Aligned Backside Contacts Made Using Dielectric Plugs") is directed at a process in which sacrificial dielectric plugs formed during frontside processing are exposed and replaced from the backside. US20260190442A1 claims a dielectric trench plug that insulates source/drain material from backside metallization, and US20260190445A1 is directed at a backside fin-isolation structure with an inverse-tapered profile. Two more, US20260190467A1 on memorized source-drain strain and US20260190460A1 on multi-threshold gate "tubs," round out a portfolio directed at the same GAA platform from the channel, the threshold, and the backside.

What the record shows, and what it does not

The factual summary is narrow by design. Intel (INTC) is the named assignee on all of these records, each published July 2, 2026, each a version A1 application. The hero, US20260190475A1, is directed to a CMOS pair with non-coplanar GAA stacks, claimed as apparatus and as method, with dependent claims reaching mixed silicon and germanium-family channels, opposing work-function metals, and unequal sheet counts, classified under H10D 84/856 and neighboring subclasses. The companions are directed to backside contacts, backside isolation, strain memory, and per-device threshold tuning. That is the coverage these filings describe.

What the record does not show is worth stating plainly. These are published applications; none is a granted patent, and the claims that eventually issue — if any do — may be narrower than the language published this week. The non-coplanar limitation, the material pairing, and the sheet-count mismatch are what the applications claim, not findings about what is enforceable, novel, or in production. Nothing here identifies which products, if any, practice these structures. For an IP reader tracking the leading-edge logic thicket, the value of a pub drop is exactly this: it shows, in the assignee's own claim language, what Intel is currently reaching to cover in gate-all-around CMOS and backside power — down to the plane the channel sits in. For the engineering context of the disclosed device, chipdocket walks the structure; for what the filing cadence suggests commercially, hardwareledger reads the same drop.