Burying interconnect lines beneath the active devices - rather than routing them above - frees up surface area and shortens connections, a technique gaining ground in both logic backside power and DRAM. Nanya Technology Corporation, the Taiwanese DRAM maker, claims a method making both buried power and buried signal lines in a single structure in its mid-2023 grant.
US11647623B2, "Method for manufacturing semiconductor structure with buried power line and buried signal line" (issued 2023-05-09), is classified in H10B 12/20 (DRAM with buried/recessed elements) with H01L 21/743 (trench formation) and H01L 23/535 (power interconnect). The claim covers fabricating both a buried power line and a buried signal line within one structure.
Construe the dual-buried limitation. Burying one line is one thing; the claim's novelty is forming both power and signal buried lines together, which requires a fabrication sequence that builds the two at different depths or in different regions without shorting them. The method's specific integration is what is fenced.
The design-around space is in the fabrication sequence and the line arrangement. A competitor burying only power (backside-power style) and routing signal on the surface, or using a different trench-and-fill order, reaches comparable area savings outside a claim requiring both lines buried by this method.
Nanya's position is that of a DRAM maker scaling its periphery and array logic. Buried interconnect is a lever for shrinking the support circuitry around the memory array, and owning the dual-buried method protects Nanya's specific route. It is process IP tied directly to the company's product.
For a portfolio analyst, this grant places Nanya - often overlooked next to Samsung, SK hynix, and Micron - as an active filer in DRAM interconnect scaling. The buried-line thicket spans the DRAM makers and the equipment vendors, and Nanya's method claims are part of the competitive picture in trench-based interconnect that any DRAM scaling effort should map.