Burying interconnect lines beneath the active devices — rather than routing them above — frees up surface area and shortens connections, a technique gaining ground in both logic backside power and DRAM. Nanya Technology Corporation, the Taiwanese DRAM maker, claims a method making both buried power and buried signal lines in a single structure in its mid-2023 grant.

US11647623B2, "Method for manufacturing semiconductor structure with buried power line and buried signal line" (issued 2023-05-09), is classified in H10B 12/20 (DRAM with buried/recessed elements) with H01L 21/743 (trench formation) and H01L 23/535 (power interconnect). The claim covers fabricating both a buried power line and a buried signal line within one structure.

“A method of fabricating a semiconductor structure, comprising: providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line.”— U.S. Patent No. 11,647,623 source

Construe the dual-buried limitation. Burying one line is one thing; the novelty of independent claim 1 is forming both the power line and the signal line from a single conductive material disposed into a recess in the active region, with that recess defined inside an isolation region that surrounds the active area. The same recess-and-fill step yields both buried lines, which is what makes the integration economical — but it also means the method has to keep the two electrically distinct as the structure builds upward.

The claim then ties those buried lines into a DRAM cell, and that is where the grounding tightens. Claim 1 forms a first circuit layer and a second, separated circuit layer on the top surface, with the first circuit layer covering the buried power and signal lines, and then forms a cell capacitor over that first circuit layer. Claim 2 adds a word-line structure over the capacitor and an interlayer dielectric encapsulating both. Claims 3 and 4 open a through-hole penetrating that dielectric to partially expose the second circuit layer and fill it with a second conductive material. Claim 5 forms a bit-line structure on the dielectric over the word line, and claims 6 and 7 make that bit line electrically coupled to the word line, the cell capacitor, and (claim 7) the first circuit layer — while claim 8 has the second conductive material connect the bit line down to the second circuit layer. The sequence describes a full buried-interconnect-to-cell stack, not just a pair of trenches.

What gives the claim its DRAM-specific character is the order in which those elements are built and connected, traced through the dependent chain. After the buried power and signal lines are filled into the active-region recess and the two separated circuit layers are formed (the first covering the buried lines), the cell capacitor goes on top of the first circuit layer, then the word-line structure goes over the capacitor, then an interlayer dielectric encapsulates capacitor and word line (claim 2). Only afterward is a through-hole etched down through that dielectric to land on the second circuit layer (claim 3) and filled with a second conductive material (claim 4) — the vertical link that will later tie the surface bit line back down to the buried-line plane. The bit line itself is formed last, on the dielectric and over the word line (claim 5), and is wired to the word line, the capacitor, and the first circuit layer (claims 6—7), with claim 8 routing it through the second conductive material to the second circuit layer. In other words the buried power and signal lines are not free-floating — the method specifies exactly how each is reached from the surface bit and word lines through the two circuit layers and the through-hole via. That connection scheme, not merely the existence of two buried lines, is the inventive heart.

The design-around space is in the fabrication sequence and the line arrangement. A competitor burying only power (backside-power style) and routing signal on the surface, or forming the two buried lines from separate fills rather than one common conductive disposition, or connecting the cell capacitor and bit line through a different layer order, reaches comparable area savings outside a claim that turns on the single-recess dual-line fill feeding the recited circuit-layer-capacitor-word-line-bit-line stack.

The classification places the patent squarely in DRAM rather than generic interconnect: the lead code H10B 12/20 is memory devices with buried or recessed elements — the modern code for capacitor-DRAM with buried structures — supported by H01L 21/743 for the recess/trench formation step that opens the active-region recess, and H01L 23/535 for the power-interconnect line itself. That combination matches a claim whose two buried lines (one power, one signal) are formed by a trench-and-fill and then knitted into a capacitor cell. It is a single-independent-claim patent (claim 1) with a short dependent chain, so the scope is comparatively easy to construe: a competitor either follows the recess-fill-dual-line-then-cell sequence with the recited circuit-layer and through-hole connections, or it does not. For a DRAM scaling roadmap, the value is knowing that this particular buried-power-plus-buried-signal route, tied to a capacitor cell, carries a Taiwanese DRAM-maker grant from 2023.

Nanya's position is that of a DRAM maker scaling its periphery and array logic. Buried interconnect is a lever for shrinking the support circuitry around the memory array, and owning the dual-buried method — together with how those lines are tied through the circuit layers into the capacitor and bit line — protects Nanya's specific route. It is process IP tied directly to the company's product.

For a portfolio analyst, this grant places Nanya — often overlooked next to Samsung, SK hynix, and Micron — as an active filer in DRAM interconnect scaling. The buried-line thicket spans the DRAM makers and the equipment vendors, and Nanya's method claims, with their detailed cell-integration steps, are part of the competitive picture in trench-based interconnect that any DRAM scaling effort should map.