What does a backside power delivery network (BSPDN) patent claim, and how is it classified? A BSPDN design relocates a chip's power and ground distribution away from the crowded front-side back-end-of-line metal stack and onto a separate metal network fabricated on the thinned backside of the wafer. The transistors are connected to that backside network by buried power rails — conductive lines sunk into the silicon that extend down to, or through, the wafer's backside. The patents in this area claim the structures that make that connection: the buried rail, the through-substrate via, and the backside metal layer they join. In the Cooperative Patent Classification (CPC) scheme, the on-chip power and ground distribution sits at H01L 23/5286, which the USPTO titles "Arrangements of power or ground buses," and the connection that passes through the substrate is classified at H01L 23/481, "Internal lead connections, e.g. via connections, feedthrough structures." The two codes together describe the BSPDN: a power bus, plus a feedthrough to reach it from the back.

A 2026 grant makes the claim structure concrete. International Business Machines Corporation holds US Patent 12,568,814 (issued March 3, 2026), titled "Buried power rail directly contacting backside power delivery network." Its independent claim 1 recites:

A semiconductor structure comprising: a via connected to a buried power rail extending below a backside of a semiconductor substrate, wherein the via and the buried power rail are composed of a single metal material, wherein the via surrounds a bottom portion of the buried power rail extending below the backside of the semiconductor substrate.— US 12,568,814 B2, claim 1, source

Three limitations carry the scope of that claim. First, "a buried power rail extending below a backside of a semiconductor substrate" — the rail does not stop at the device layer; it reaches through to the backside, which is what lets a backside network power the transistors. Second, "the via and the buried power rail are composed of a single metal material" — the via and rail are one continuous metal, not two metals joined at an interface. Third, "the via surrounds a bottom portion of the buried power rail" — the backside via wraps the protruding bottom of the rail rather than landing on its flat end. Claim 6 explains why that geometry is recited: the surrounding via "reduces contact resistance between the via and the buried power rail," and the structure has no liner. For a claim-construction read, the single-metal, surrounding-via geometry is the limitation that distinguishes this claim from a conventional two-metal via landing on a rail.

What the dependent claims reveal about the process

The dependents track how a BSPDN is actually built. Claim 2 recites that the via "is in a first metal layer of a backside power delivery network" — naming the backside network explicitly. Claim 7 recites that the bottom of the rail extending below the backside "is a nanoscale through-silicon via," tying the buried-rail concept to the through-silicon-via family while keeping it at sub-conventional dimensions. The method claims (16 through 18) walk the fabrication sequence: forming the buried rail from the front side, bonding a carrier wafer, thinning the substrate so the rail "extends beyond a surface of a backside," then etching dielectric to expose the rail bottom and forming the surrounding via. That sequence — front-side rail, carrier bond, backside thinning, backside via — is the canonical BSPDN flow, and reading it in the claims shows where the patentable detail sits: in the order of operations and the single-metal continuity, not in the broad idea of powering from the back.

What the second independent claim adds

The patent carries a second independent structure claim, claim 8, that recites the network from a different angle: "a plurality of buried power rails in a semiconductor substrate," with at least one rail's portion below the backside, "at least one portion of a first metal layer of a backside power delivery network" surrounding that portion, and "an interlayer dielectric material isolating" the backside metal from the substrate backside. The dielectric-isolation limitation is significant — it recites that the backside power layer is electrically separated from the bulk silicon by dielectric, which is what prevents the power network from shorting to the substrate. Claim 9 then recites that the rails and the backside metal layer "are composed of a same conductive material," and that the metal portion is "one of a group of a via, a wire, or a contact" — broadening the connection beyond a single via geometry. Claim 11 recites the rail "directly contacts a portion of the semiconductor substrate, a portion of the interlayer dielectric, and the at least one portion of the first metal layer," and that "the semiconductor substrate is thinned." For a freedom-to-operate read, claim 8 and its dependents are the broader independent path; they capture the rail-network-dielectric arrangement without requiring the single-metal surrounding-via geometry that claim 1 demands.

How the classification frames the landscape

For mapping the BSPDN landscape, the CPC codes split the structure cleanly. H01L 23/5286, "Arrangements of power or ground buses," captures the power-distribution network itself, whether front-side or backside. H01L 23/481, "Internal lead connections, e.g. via connections, feedthrough structures," captures the through-substrate connection that a backside network requires. A searcher building a portfolio map reads both: the bus arrangement tells you who is claiming the distribution topology, and the feedthrough class tells you who is claiming the connection method. The IBM grant carries both codes plus H01L 23/5226, reflecting that a buried-power-rail claim is simultaneously a power-bus claim and a feedthrough claim. That dual classification is the signal that BSPDN is a structure spanning two established CPC families rather than a wholly new class.

What the record shows is that backside power delivery, at the claim level, is about the connection geometry. US 12,568,814 claim 1 recites a buried power rail extending below the substrate backside, joined by a single-metal via that surrounds the rail's bottom — and claim 6 ties that geometry to reduced contact resistance and a linerless structure. The CPC anchors, H01L 23/5286 for the power bus and H01L 23/481 for the through-substrate feedthrough, classify the same structure from the distribution and connection sides. The broad concept of powering a chip from its backside is not what these claims protect; the specific rail-via geometry and the build sequence are. How any such claim reads against a competing backside-power design depends on that claim's exact limitations and its prosecution history.