What do gate-all-around (GAA) nanosheet transistor patents actually claim, and where do they sit in the patent classification system? A GAA patent claims a field-effect transistor in which the gate completely surrounds the conductive channel, in contrast to the FinFET, whose gate wraps only three sides of a vertical fin. The channel itself is a thin horizontal sheet of semiconductor — a nanosheet — and devices typically stack several of these sheets vertically, with the gate filling the space between them so it surrounds each one. In the Cooperative Patent Classification (CPC) scheme used by the USPTO and EPO, this device is classified at H10D 30/6735, which the USPTO titles as field-effect transistors "having gates fully surrounding the channels, e.g. gate-all-around." That subgroup sits under H10D 30/00, "Field-effect transistors [FET]." The classification confirms what the claims recite: the defining feature is the gate fully enclosing the channel.

A granted example anchors the structure. Samsung Electronics Co., Ltd. holds US Patent 9,685,564 (issued June 20, 2017), titled "Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures." Its independent claim 1 recites the geometry directly:

A Gate-All-Around (GAA) Field Effect Transistor (FET) comprising: a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, and a height that is perpendicular to the horizontal direction... first and second source/drain regions located at opposing ends of the horizontal nanosheet conductive channel structure; and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.— US 9,685,564 B2, claim 1, source

Three limitations in that claim carry the scope. First, the channel is a "horizontal nanosheet conductive channel structure" with a defined width and height — the sheet geometry, not a vertical fin. Second, source and drain sit "at opposing ends" of that sheet, the standard FET arrangement. Third, and most important, "a unitary gate material completely surrounding" the channel. That last phrase is the gate-all-around limitation: the word "completely" is what separates a GAA claim from a FinFET claim, where the gate would surround only three sides. For a reader doing claim construction, the question of whether a competing device reads on this claim turns on whether its gate, in fact, completely surrounds the channel sheet.

What the dependent claims add

The dependents in this family illustrate where additional scope lives, and they track the real engineering of stacked-nanosheet devices. Claim 2 recites that the channel "is included in a vertical stack of N horizontal nanosheet conductive channel structures," each in its own horizontal plane — the multi-sheet stack that gives a GAA device its drive current. Claim 3 adds that each of the N sheets "provides about 1/N of an effective channel width," capturing the design principle that effective width is divided across the stacked sheets. Claim 5 recites that the gate "extends horizontally between" the sheets, and claim 7 that it "seamlessly surrounds each" of them — both reinforcing that the gate fills the inter-sheet gaps. Claim 6 covers a stack in which the lowest sheet is wider than the uppermost, a tapered profile that reflects how the sheets are actually patterned. These dependents matter because the independent claim describes the device class; the dependents describe the manufacturable embodiments, and a design-around analysis works through them in order.

The inter-channel and spacing limitations

This particular family does not stop at the basic gate-all-around structure; its title points to "MOL/inter-channel spacing," and several claims build on that. Claim 8 recites a first and a second GAA FET that are "directly adjacent," with the space between the edge of one channel sheet and the corresponding edge of the next being "about equal to a Middle-Of-Line (MOL) spacing between directly adjacent source/drain regions." Claim 9 ties that MOL spacing to "a design rule space for a contact to the unitary gate material between the first and second GAA FETs," and claim 10 recites that the MOL spacing "is at least twice the vertical spacing" between sheets in the stack. The independent claim 18 reframes the whole device around that relationship: a semiconductor device defined by an MOL contact spacing "being about equal to an inter-channel spacing between the first and second horizontal nanosheet conductive channel structures." These limitations matter because, in a real cell library, the spacing between adjacent transistors and the room for a gate contact are what set cell area. A claim that ties the inter-channel spacing to the MOL contact rule is claiming a layout constraint, not just a device — and that is a different scope question than the bare gate-all-around geometry of claim 1.

Why the CPC class anchors the landscape

For anyone mapping the GAA patent landscape, the CPC code is the navigation tool. H10D 30/6735 is a 2025-dated subgroup created in the reclassification that moved most H01L 29 transistor matter into the new H10D scheme; the GAA device that Samsung's patent describes was originally also classified in the legacy H01L 29/0673 area covering nanowire/nanosheet semiconductor bodies. Reading the classification literally — "having gates fully surrounding the channels, e.g. gate-all-around" — tells a searcher that the subgroup is defined by the gate-channel geometry, the same limitation the independent claim recites. That alignment is useful: a portfolio search in H10D 30/6735 will surface the device-structure claims, while the process of building the stacked sheets sits in adjacent manufacturing subgroups such as H10D 30/01, "Manufacture or treatment." The geometry-versus-process split in the CPC scheme mirrors the structure-versus-method split in the claims themselves.

What the record shows is consistent across the classification and the claim text. The defining feature of a gate-all-around nanosheet transistor, as recited in US 9,685,564 claim 1 and as classified at CPC H10D 30/6735, is a gate that completely surrounds a horizontal nanosheet channel, with devices stacking N such sheets so the gate wraps each one. The nanosheet alone does not define the claim; the gate fully enclosing it does. For a competitive-intelligence or freedom-to-operate read, that single limitation — "completely surrounding" — is the element to test a device against, and the CPC subgroup is the field in which the comparable grants are found. How broadly any one of these claims reaches against a specific competing transistor depends on that claim's own language and its file history; the classification and the independent claim establish only what the device class is.