What does a 2-transistor memory-cell application actually claim, beyond "a smaller DRAM bit"? The answer is structural, and it is not in the title. The hero record this week, Samsung Electronics (005930.KS) application US20260181855A1 ("Semiconductor Device Comprising a 2-Transistor (2T) Memory Cell and Method of Manufacturing the Same," published June 25, 2026), is directed to a memory cell built from two transistors stacked one on top of the other, both contacting a single bit line that runs in the vertical direction. The limitation doing the work is the geometry: a first transistor and a second transistor on the first transistor, with a storage node held between their two gate electrode layers. The threshold question belongs up front: this is a published application, not a granted patent. It defines the scope Samsung is pursuing in vertical memory scaling, not scope an examiner has allowed.

Read claim 1 element by element, because the cell's whole identity lives in the relationships it recites. There is a bit line extending in a vertical direction. There is a 2T memory cell on at least one side of that bit line, made of a first transistor and a second transistor on the first transistor. The first transistor — the access device — includes an active pattern that contacts the bit line, with a first source/drain region, a second source/drain region, and a channel region between them, plus a first gate structure whose first gate electrode layer overlaps the channel region. The second transistor — the storage device — includes a second gate structure with a second gate electrode layer, and a channel structure that also contacts the bit line. That channel structure is the distinctive part: it has a first horizontal portion extending away from the bit line, and a vertical portion extending vertically from one end of that horizontal portion. Between the first and second gate electrode layers sits a storage node, connected to the channel structure. That sandwiched storage node, bounded by the two gate electrodes, is the limitation that defines this cell rather than a generic stacked pair of transistors.

A bit line extending in a vertical direction; and a 2-transistor (2T) memory cell on at least one side of the bit line, the 2-transistor (2T) memory cell including a first transistor and a second transistor on the first transistor … and a storage node between the first gate electrode layer and the second gate electrode layer, and the storage node connected to the channel structure.— Semiconductor Device Comprising a 2-Transistor (2T) Memory Cell and Method of Manufacturing the Same, US20260181855A1

Why does stacking two transistors on a vertical bit line matter as claimed structure? A conventional DRAM bit is one transistor plus one capacitor (1T1C) laid out across the silicon surface, and shrinking it has run into the physics of building a deep capacitor in ever-smaller footprints. The cell this application is directed to instead spends its area in the third dimension: by putting the storage transistor on top of the access transistor and routing both to a bit line that runs vertically, the footprint per bit is set by the stack, not by a side-by-side capacitor. The dependent claims sharpen what kind of cell this is. Claim 8 recites that the access transistor's channel region includes silicon while the storage transistor's channel structure is an oxide semiconductor; claim 7 recites that the storage node itself can be a metal or an oxide semiconductor and the channel structure an oxide semiconductor. The pairing of a silicon access device with an oxide-semiconductor storage device is the signal that this is a gain-cell-style memory aimed at low leakage at the storage node, where oxide-semiconductor transistors are valued for very low off-state current. For an IP reader, scope here is built from those material and geometric limitations, not from the bare idea of a 2T cell.

Where it lands in the CPC landscape

The classification tells you which neighborhood the application is filed into, and it is not the packaging neighborhood. US20260181855A1 is directed at memory scaling and lands in the main CPC group H10B 12/00 — the dynamic random-access memory (DRAM) territory of the reorganized H10B "electronic memory devices" space. That is the deliberate distinction this filing draws against the rest of the week's Samsung drop, much of which sits in the H10W advanced-packaging and assembly subclasses: this cell is about shrinking the bit itself at the device level, not about bonding or stacking finished dies. The independent claims reinforce the read. Claim 16 recites a plurality of 2T memory cells arranged vertically on a substrate, each with an insulating material layer between its two transistors — the array-level expression of the same stacked-cell idea. Claim 19 recasts the cell around a first transistor whose active pattern carries a first channel region and a second transistor whose second channel region has horizontal and vertical portions, with a storage node vertically overlapping the first channel region. Three independent claims, one structural thesis: stack the two transistors and fold the storage node between their gates.

The companion records in the same June 25 publication window classify into adjacent corners of the memory and device map, which is what makes this a cluster read rather than a one-off. US20260181914A1 ("Semiconductor Device and Data Storage System Including Semiconductor Device") is directed to a vertical stack structure with gate electrodes spaced apart vertically and a channel structure running through a channel hole, incorporating a resistance-switching layer whose conductivity varies with an oxygen-ion electrochemical reaction — a different, resistive memory architecture in the same vertical-scaling vein. US20260181913A1 ("Method for Manufacturing Semiconductor Memory Device Including Forming Conductive Line") claims a fabrication sequence that builds a first electrode, an information-storage pattern, and a second electrode between two conductive lines — the cross-point memory-cell process flow. US20260182026A1 ("Semiconductor Device") is directed to a transistor whose channel layer is a p-type oxide semiconductor containing tin and tellurium with an oxygen-deficient composition — the materials layer beneath the kind of oxide-semiconductor channel the hero cell recites.

Three more fill out the device-architecture side of the cluster. US20260182021A1 ("Semiconductor Device Including Separation Pattern") is directed to a stacked structure with lower and upper channel and source/drain patterns and a separation pattern penetrating the gates. US20260182015A1 ("Semiconductor Device") claims a related stacked-channel device with a gate-cutting pattern and a through-via penetrating it. US20260181955A1 ("Semiconductor Devices Including Gate-All-Around Type Field Effect Transistor") is directed to a gate-all-around transistor whose uppermost channel layer is split into separated channel portions below the gate spacers. Read together, the drop describes Samsung working the same vertical-integration problem across DRAM, resistive memory, oxide-semiconductor materials, and stacked-channel logic.

What the record shows, and what it does not

The factual summary is narrow by design. Samsung Electronics (005930.KS) is the named assignee on each of these records, all published June 25, 2026, each a version A1 application. The hero, US20260181855A1, is directed to a 2-transistor memory cell whose two transistors are stacked on a single vertical bit line, with a silicon-channel access transistor, an oxide-semiconductor storage transistor whose channel structure has horizontal and vertical portions, and a storage node held between the two gate electrode layers — classified under H10B 12/00 (DRAM). The companions are directed to vertical resistive memory, cross-point cell fabrication, oxide-semiconductor channel materials, and stacked-channel device structures. That is the coverage these filings describe.

What the record does not show is equally important to state plainly. These are published applications; none is a granted patent, and the claims that eventually issue — if any do — may be narrower than the language published this week. The vertical-bit-line geometry, the horizontal-and-vertical channel structure, and the silicon-plus-oxide-semiconductor material split are what the application claims, not findings about what is enforceable, novel, or commercially deployed. Nothing here speaks to which products, if any, practice these cells, or to any roadmap node. For an IP reader tracking the memory-scaling thicket, the value of a pub drop is exactly this: it shows, on the public record and in the assignee's own claim language, what Samsung is currently reaching to cover in vertical 2T memory — two transistors, one bit line, and a storage node folded between the gates.