The two leading 2.5D packaging approaches - a full silicon interposer versus localized embedded bridges (EMIB) - are usually framed as alternatives. Intel Corporation's early-2024 grant claims using both in one package, combining the interposer's broad routing reach with the bridge's localized density.
US11901299B2, "Interconnect architecture with silicon interposer and EMIB" (issued 2024-02-13), is classified in H01L 23/5385/5386 (internal connections) with H01L 24/16/17 (bumps), H01L 25/18, and H01L 23/481 (TSV). The claim covers an architecture that includes both a silicon interposer and an embedded multi-die interconnect bridge.
Construe the combination limitation. Each element is known; the claimed novelty is the architecture that uses an interposer for some connections and EMIB for others within the same package. The independent claim specifies how the interposer and bridge divide the interconnect duty - which connections route through which medium.
The strategic rationale is scale. The largest AI packages exceed the size a single interposer can economically cover, so combining a (possibly smaller or segmented) interposer with embedded bridges extends reach while controlling cost. The claim defends that hybrid topology.
The design-around space is in the partitioning. A competitor using interposer-only (TSMC CoWoS-S) or bridge-only (classic EMIB), or TSMC's CoWoS-L which reconstitutes bridges in a molded interposer, reaches large-package integration by a different route. Intel's claim fences specifically the silicon-interposer-plus-EMIB combination.
For competitive intelligence, this grant signals Intel preparing packaging for very large multi-die products - the kind of system-in-package that AI training silicon demands. It rounds out Intel's bridge and interposer portfolio into a hybrid story, and anyone designing a giant multi-die package should know Intel has fenced the interposer-plus-bridge combination.