The two leading 2.5D packaging approaches — a full silicon interposer versus localized embedded bridges (EMIB) — are usually framed as alternatives. Intel Corporation's early-2024 grant claims using both in one package, combining the interposer's broad routing reach with the bridge's localized density.

US11901299B2, "Interconnect architecture with silicon interposer and EMIB" (issued 2024-02-13), is classified in H01L 23/5385/5386 (internal connections) with H01L 24/16/17 (bumps), H01L 25/18, and H01L 23/481 (TSV). The claim covers an architecture that includes both a silicon interposer and an embedded multi-die interconnect bridge.

“Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coup…”— U.S. Patent No. 11,901,299 source

Construe the combination limitation. Each element is known; the claimed novelty is the architecture that uses an interposer for some connections and EMIB for others within the same package. Independent claim 1 recites a package substrate, an interposer on it carrying a first and a second die stack coupled by conductive traces, a separate die on the package substrate, and an interconnect bridge on the substrate that electrically couples the interposer to that separate die. The bridge, in other words, is what stitches the bumped-out peripheral die into the interposer's fabric rather than the interposer reaching it directly.

The dependent claims pin down what divides the interconnect duty, and this is where the real grounding lives. Claim 5 specifies a three-tier pitch hierarchy: first interconnects coupling the die stacks to the interposer at a first (fine) pitch, second interconnects coupling the interposer and the die to the bridge at a larger second pitch, and third interconnects coupling the interposer to the package substrate at a larger third pitch — with all three permitted to be solder or copper-to-copper joints. That graded pitch is the physical expression of the architecture's logic: the densest connections ride the interposer, coarser ones cross the bridge, and the coarsest drop to the organic substrate. Claim 3 ties each die stack to an IC base die with memory dies stacked over it, and claim 4 lets those memory dies overhang a smaller base-die footprint.

The strategic rationale is scale. The specification frames the problem directly: HPC processors use the largest manufacturable die, roughly 600—800 mm², and stacking an array of six to eight roughly-100 mm² DRAM dies over such a die hurts yield (a single bad chip kills the part) and thermal transfer. Partitioning into independently testable "die cubes" of FPGA base plus stacked DRAM, knit together on an interposer and extended by bridges, lets known-good subassemblies be combined. Claims 11 and 23 push further, reciting multiple interposers stitched together by additional bridges — the route to packages larger than any single interposer can economically span. The claim defends that hybrid topology.

The second independent claim, claim 11, restates the architecture in array form: a package substrate, a first interconnect bridge on it, a first interposer carrying a first plurality of die stacks, and a first die coupled to the interposer through the bridge. Its dependents scale the array — claim 12 a 2×2 array of die stacks, claim 13 a general M×N array (M and N each one or more), claim 14 coupling those stacks through interposer traces. Claim 15 adds a second interposer coupled to the first by a second bridge, and claim 17 even lets a die stack straddle two interposers — the explicit mechanism for tiling interposers into an arbitrarily large fabric. Claim 19 names the bridged peripheral die as a high-bandwidth memory, an in-package memory die, or a transceiver, and claim 23 ties the whole picture together: silicon interposer, FPGA die stacks coupled by interposer traces at a fine first pitch, and a peripheral die bridged in at a larger second pitch. Claim 24 has the FPGA at a more advanced process node than the bridged die — capturing the reuse rationale, that older-node transceiver and HBM dies can be bridged into a package built around leading-node compute.

The design-around space is in the partitioning. A competitor using interposer-only (TSMC CoWoS-S) or bridge-only (classic EMIB), or TSMC's CoWoS-L which reconstitutes bridges in a molded interposer, reaches large-package integration by a different route. Intel's claim fences specifically the silicon-interposer-plus-EMIB combination, including the graded-pitch interconnect scheme and the interposer-to-interposer bridging in the dependent claims; avoiding it means avoiding that particular division of labor, not merely the goal of a big multi-die part.

The CPC placement reinforces where the boundary sits. H01L 23/5385/5386 covers the internal package connections — the interposer traces and bridge wiring — while H01L 25/18 is the assembly of devices into a package and H01L 23/481 is the through-silicon-via path that lets the die cubes stack DRAM over a base die. The bump codes H01L 24/16/17 are where the graded-pitch interconnect limitation lives. A package that achieved large-die integration but landed only in, say, the molded-interposer codes (TSMC's CoWoS-L direction) or pure-bridge codes without the on-substrate silicon interposer would read on a different part of the classification map. The patent is a continuation of a 2018 application, so its priority reaches back before much of the current AI-package buildout — a date worth noting for anyone assessing prior art in interposer-plus-bridge packaging.

For competitive intelligence, this grant signals Intel preparing packaging for very large multi-die products — the kind of system-in-package that AI training silicon demands. It rounds out Intel's bridge and interposer portfolio into a hybrid story, and anyone designing a giant multi-die package should know Intel has fenced the interposer-plus-bridge combination, the staged-pitch interconnect, and the multi-interposer extension claimed here.