What does a hybrid-bonding patent application actually claim, beyond "we stack two chips and bond them"? The interesting answer is almost never in the title. The hero record this week, Samsung Electronics (005930.KS) application US20260173964A1 ("Semiconductor Device," published June 18, 2026), is directed to a die-to-die bonded structure whose distinguishing limitation is a number: a mean grain size, for each of the two bonded copper pads, in the range of 25 nm to 70 nm. That grain-size window is the limitation doing the work. The rest of the claim describes geometry that the field already knows; the metallurgy is where the application stakes its territory. Note the threshold question up front: this is a published application, not a granted patent. It defines the scope Samsung is pursuing, not scope an examiner has allowed.

Read the structure the application is directed to, element by element. There is a first semiconductor die carrying a first pad and a first adhesive layer that covers the upper portion of the pad's side wall; a second die carrying a second pad and a second adhesive layer that covers the lower portion of that pad's side wall; and a first protection layer interposed between the first pad and the second adhesive layer. The application recites that the second pad sits on the first pad, that a top surface of the first pad has a portion exposed by the second pad, and that the second adhesive layer lands on that exposed portion. This is the anatomy of copper-to-copper hybrid bonding, where the metal pads form a direct conductive joint and the surrounding dielectric or adhesive forms the bond elsewhere, all without solder bumps between the dies. The exposed-pad and protection-layer language is the application's way of describing how the two pads meet without the surrounding adhesive contaminating the metal interface.

A mean grain size of each of the first pad and the second pad may range from 25 nm to 70 nm. The second pad may be on the first pad, a top surface of the first pad may include a portion exposed by the second pad, and the second adhesive layer may be on the exposed portion of the first pad.— Semiconductor Device, US20260173964A1

Why does the grain size matter as a claim limitation? In hybrid bonding, the copper pads are joined and then annealed; the copper grows and the two pads merge into a continuous conductor across the interface. The grain structure of the deposited copper governs how that anneal behaves, so reciting a bounded mean grain size is a way of claiming a metallurgical state of the bonded pad rather than only its shape. For an IP reader, the practical consequence is navigational: a numeric range like 25–70 nm is the kind of limitation that defines where this application's coverage begins and ends. The application is directed to copper within that band; it does not, on its face, reach pad metallurgy outside it. Whether any of this survives examination unchanged is a separate question the public record does not yet answer.

Where it lands in the CPC landscape

The classification tells you what neighborhood the application is filed into. US20260173964A1 carries CPC symbols including H10W 80/312 and H10W 80/327, which sit in the bonding-and-interconnect region of the reorganized H10W space for semiconductor device assemblies, alongside H10W 90/297 and H10W 90/792. For readers still mapping the old codes, this is the territory that the former H01L24 "bonding" group covered — ball/bump/pad bonding, the connective tissue of advanced packaging. The presence of the H10W 80/3xx bonding subclasses, rather than only the H10W 90/xx assembly subclasses, is the signal that the application is directed at the metal-join itself and not merely at the surrounding package. That is consistent with a grain-size limitation: a filing about how copper pads bond will classify into the bonding subclasses.

The companion records in the same publication window classify into adjacent corners of the same map, which is what makes this read a cluster rather than a one-off. US20260173976A1 ("Semiconductor Package and Method for Fabricating the Same") is directed to a semiconductor stack of core dies sequentially stacked with an offset between adjacent dies, each connected through vertical wires to conductive posts on a redistribution structure — the staircase-and-wire geometry familiar from stacked-memory packaging. US20260173984A1 claims a related package in which chips are stacked within a sealing member and joined by conductive wires running substantially vertically from the molding surface to the chip pads and a separate bonding pad. US20260173967A1 is directed to a stacked package whose lower chip carries redistribution patterns and chip-connecting pads separated by a trench in an enclosing insulating layer.

Two more fill out the cluster on the through-silicon side. US20260173969A1 ("Semiconductor Package and Method of Manufacturing Semiconductor Package") is directed to a fabrication sequence built around through-electrodes in a substrate, a back-side insulating layer with etched grooves, and successive barrier and conductive material layers — the back-side processing that stacked dies require to route signals vertically. US20260173929A1 claims a semiconductor chip with a through-via penetrating the substrate to connect to a wiring line, plus front- and back-side passivation layers and conductive pads, and recites a thickness relationship in which a first passivation layer is 0.4 to 0.6 times a defined stack thickness — another instance of a numeric limitation carrying the claim. Read together, six applications in one drop describe the same problem from different angles: how to join and route stacked dies, pad by pad and via by via.

What the record shows, and what it does not

The factual summary is narrow by design. Samsung Electronics (005930.KS) is the named assignee on all six records, each published June 18, 2026, each a version A1 application. The hero, US20260173964A1, is directed to a hybrid-bonded two-die structure with a recited mean copper-pad grain size of 25–70 nm, an exposed-pad geometry, and an interposed protection layer, classified under the H10W 80/3xx bonding subclasses. The companions are directed to stacked packages, vertical-wire interconnects, and through-electrode routing in the surrounding H10W 90/xx assembly subclasses. That is the coverage these filings describe.

What the record does not show is equally important to state plainly. These are published applications; none is a granted patent, and the claims that eventually issue — if any do — may be narrower than the language published this week. The grain-size range, the thickness ratio, and the exposed-pad limitations are what the applications claim, not findings about what is enforceable, novel, or commercially deployed. Nothing here speaks to which products, if any, practice these structures. For an IP reader tracking the advanced-packaging thicket, the value of a pub drop is exactly this: it shows, on the public record and in the assignee's own claim language, what Samsung is currently reaching to cover in copper-pad bonding and stacked-die routing — down to the grain.