High-bandwidth memory earns its name through parallelism: an HBM stack exposes many independent channels, and aggregate bandwidth is the product of channel width, clock, and how many channels you can keep busy at once. Organizing the stack into ranks - groups of memory accessed together - is one lever on that. XILINX, INC.'s 2021 grant claims a multi-rank HBM scheme.
US11189338B1, "Multi-rank high bandwidth memory (HBM) memory" (issued 2021-11-30), is classified in G11C 11/4096 (DRAM addressing/control) with H01L 25/18 (assemblies of memory devices), H01L 24/08/09, and interposer-interconnect subclasses H01L 2224/16xxx. The claim ties the rank organization to the physical interconnect between the HBM stack and the host die across an interposer.
Construe the limitation. Multi-rank organization existed in conventional DRAM long before HBM, so the claim cannot be on ranks per se. Its value is in the specific arrangement of ranks within the HBM stack and how those ranks map onto the interposer interconnect to the FPGA or accelerator. The structural coupling of rank logic to 2.5D interconnect is the distinguishing feature.
The design-around space sits in the addressing and the physical mapping. A competitor organizing HBM ranks differently, or distributing them across the interconnect with another topology, can reach comparable parallelism outside this claim's literal scope.
The assignee context matters: Xilinx (acquired by AMD in 2022) shipped FPGAs with integrated HBM well ahead of the general AI-accelerator wave. This patent defends the integration know-how that made those parts competitive, and it now sits inside AMD's broader memory-integration portfolio.
For a portfolio analyst, this is a reminder that the HBM IP landscape is not only the memory makers (Samsung, SK hynix, Micron) but also the integrators who attach HBM to logic - Xilinx/AMD, NVIDIA, Intel. The rank-and-interconnect claims live with the integrators, not the DRAM vendors.