For decades, memory got denser by shrinking cells laterally. That route is exhausting, so density now scales vertically — stacking storage in the third dimension. But there is more than one way to go up, and the June 2026 record shows two assignees fencing two distinct routes. Mapping that split is the key to the modern vertical-memory thicket.
Micron Technology, Inc.'s US12651628B2, "Microelectronic devices and memory devices including vertically spaced transistors and storage devices" (issued 2026-06-09), takes the structural route. Its classifications — G11C 11/4085/4091/4097 (DRAM operation) with H10B 12/315/482/485/50 (DRAM device structure) — describe a cell in which the access transistor and the storage element are vertically spaced rather than side by side. The limitation that matters is "vertically spaced": the patent claims the stacked-cell geometry, the route that lets a DRAM bit shrink its footprint by going up.
Monolithic 3D Inc.'s US12653021B2, "Methods for fabricating 3D memory devices and structures with memory arrays and metal layers" (2026-06-09), takes the process route. Its classifications span H10B 10/12, 12/02, 43/10, 43/20 (multiple memory-device families) plus H10W 20/43/435 (3D integration), and it is a method claim. The distinction from Micron is sharp: Micron claims what the stacked cell is; Monolithic 3D claims how you build a memory stack — sequentially forming memory arrays and the metal layers between them in a true monolithic process, rather than bonding pre-made wafers.
That structure-versus-method split is the spine of the thicket. A device claim (Micron) is infringed by anyone who ships the claimed stacked cell, regardless of how they made it. A method claim (Monolithic 3D) is infringed by anyone who uses the claimed monolithic build sequence, regardless of the exact cell that results. The two can coexist precisely because they catch different infringers — a memory maker could, in principle, build a Micron-style stacked cell using a non-monolithic (wafer-bonding) process and touch one claim but not the other.
The white space sits in the gap between them. Neither claim, as classified in this batch, clearly fences the hybrid route — a vertically spaced cell built by bonding rather than monolithic fabrication — which is exactly the route a wafer-bonding-strong player like a foundry partner might pursue. That is where a CI team should expect the next filings.
The practical guidance for freedom-to-operate: a vertical-memory product has to be cleared twice — once on the cell structure (does it read on Micron's vertically-spaced geometry?) and once on the fabrication route (does it use a monolithic build like Monolithic 3D's method?). Clearing one does not clear the other, and the June 2026 grants show the two routes are owned by different assignees.