Every modern SoC mixes transistor flavors: high-performance, low-leakage, and standard threshold-voltage (Vt) devices coexist on one die so designers can spend power only where they need speed. Doing this in a gate-all-around (GAA) architecture is harder than in planar or FinFET, because the gate wraps the channel completely. International Business Machines Corporation's mid-2020 grant tackles it with a common-gate approach.

US10700064B1, "Multi-threshold voltage gate-all-around field-effect transistor devices with common gates" (issued 2020-06-30), is classified in H01L 27/088 (FET integrated circuits) with H01L 21/823412 and H01L 29/78. The claim's distinguishing feature is in the title: multiple Vt values are realized while the devices share a common gate structure, rather than building physically separate gate stacks for each Vt class.

“Devices and methods are provided to fabricate multi-threshold voltage gate-all-around field-effect transistor devices (e.g., nanosheet field-effect transistor devices) wherein threshold voltage tuning is achieved by adjusting a channel spacing between active channel layers of the gate-all-around fie…”— U.S. Patent No. 10,700,064 source

Construe what 'common gates' forces. If the gate is shared, the Vt differentiation has to come from somewhere else - channel doping, nanosheet thickness, or work-function metal variation within the shared stack. The independent claim's value is in pinning down which of these mechanisms it requires, because that determines what a competitor must avoid.

The design-around analysis follows directly. A foundry that achieves multi-Vt by patterning genuinely separate gate stacks for each device class - the more conventional FinFET-era approach - operates outside a claim that requires a common gate. The IBM claim is valuable precisely because the common-gate route saves masks and area, so designing around it means giving up that efficiency.

This is characteristic IBM Research portfolio behavior: solve a near-term manufacturing pain point (Vt tuning under GAA's geometric constraints) and patent the elegant route, leaving the brute-force route to competitors. The value is realized through licensing and cross-licensing rather than IBM shipping the node itself.

For an R&D strategist evaluating GAA Vt schemes, this grant is a marker. It says the common-gate multi-Vt approach has prior-art coverage from 2020, and any 2nm-era design using it needs a freedom-to-operate read against IBM's family.