The record under construction here is US20260206554A1, published on July 16, 2026 and assigned to Taiwan Semiconductor Manufacturing Company, Ltd. It is an A1 publication — an application laid open for inspection. It has not been examined to allowance, and nothing about its appearance in this week's drop suggests it has been. The claims below are what the applicant is asking for, not what it holds.

There are twenty claims and two of them are independent: claim 1 and claim 11. Take claim 1 first, because its structure is unusual in a way that rewards reading it slowly. It is a method claim, and it recites five acts: forming a first metal silicide layer on the front-side of an epitaxial source/drain region of a transistor; implanting a dopant into that region from the back-side; performing a nanosecond laser annealing (NSA) process on the region from the back-side; forming a second metal silicide on the back-side; and forming a back-side contact over that second silicide. Method claims frequently leave step order to the reader. This one does not. The implanting step is expressly conditioned — it occurs after forming the first metal silicide layer. That temporal limitation is written into the independent claim, not left to a dependent, which means the claim does not read on a process that implants and anneals before the front side has been silicided.

The ordering carries the technical weight. By the time the back-side is being worked, the front side is a finished, heat-sensitive stack. So the anneal has to be one that reaches the back-side surface without soaking what is above it. That is the constraint the specification describes the NSA process as answering — short-wavelength light absorbed at the surface, a pulse short enough that the heat does not travel. The abstract puts the affected depth at about 10 nanometers from the surface. That figure is a heating depth, not a device dimension; it says nothing about linewidth or geometry.

What claim 11 recites, and one wrinkle in it

Claim 11 is the second independent claim and it is drafted around a specific device context: epitaxial structures on opposite sides of a semiconductive nanostructure, with a gate structure wrapping around that nanostructure and sitting between the epitaxial structures. From there it tracks the same logic — front-side silicide first, then an amorphous region formed from the back-side surface toward the front-side surface, then the NSA process performed on that amorphous region from the back-side, then a metal silicidation process that converts what remains into a second metal silicide layer, and a metal contact over it.

One drafting artifact is worth flagging for anyone parsing this claim, because it is in the source and any accurate reproduction will carry it. Claim 11 refers to the thinned amorphous region at the silicidation step, but no preceding step in the claim recites a thinning act to introduce that term — the recited NSA step says the process recrystallizes the amorphous region. The thinning appears elsewhere in the record: the abstract describes the anneal as recrystallizing part of the amorphous region while thinning the remainder, and claim 12, which depends from claim 11, recites the NSA process being performed to thin the amorphous region's thickness to less than half its initial thickness. This is an observation about the text as published, nothing more. Here is the claim as the record has it:

A method, comprising: forming a plurality of epitaxial structures on opposite sides of a semiconductive nanostructure; forming a gate structure wrapping around the semiconductive nanostructure and between the epitaxial structures; forming a first metal silicide layer on a front-side surface of one of the epitaxial structures; after forming first metal silicide layer, forming an amorphous region extending from a back-side surface of the one of the epitaxial structures toward the front-side surface of the one of the epitaxial structures; performing a nanosecond laser annealing (NSA) process on the amorphous region from the back-side surface of the one of the epitaxial structures, wherein the NSA process recrystallizes the amorphous region; performing a metal silicidation process on the thinned amorphous region, such that the thinned amorphous region is converted to a second metal silicide layer; and forming a metal contact over the second metal silicide layer.— BACK-SIDE IMPLANTATION AND NANOSECOND LASER ANNEALING FOR SOURCE/DRAIN REGIONS, US20260206554A1

Note what claim 11 does not do: it never recites a laser wavelength, an energy density, a temperature, or a dopant species. Neither does claim 1. Every number in this record lives in a dependent claim, and dependents describe particular embodiments rather than the outer edge of what is claimed. The parameter envelope, by claim number, runs like this. Claim 2 puts the NSA laser's wavelength at less than about 400 nm. Claim 3 puts the implanted dopant's atomic concentration above roughly 1×10²¹ atoms per cubic centimeter within the back-side of the source/drain region. Claim 4 gives the NSA process an energy density in a range from about 0.5 to 1.3 J/cm². Claim 5 puts the surface heating temperature above about 700°C. Claims 6 and 7 pair a p-type source/drain carrying roughly 60–80% germanium with a gallium dopant; claims 8 and 9 pair an n-type source/drain carrying roughly 6–10% phosphorus with arsenic. Claim 10 names a nanosheet field-effect transistor as the transistor — an option, not a requirement, since claim 1 says only "a transistor." The hedges throughout ("about," "in a range from about," "can") are the applicant's, and they are load-bearing; a reader who drops them is reading a different document.

Classification and the surrounding records

The record's CPC assignments include H10P 95/90, H10D 30/014, H10D 30/0191, H10D 62/121 and H10D 64/017, among others — a mix keyed to device fabrication and source/drain formation rather than to laser equipment. That placement is consistent with what the claims do: the record does not claim nanosecond laser annealing, which is an established technique, but a particular application and sequence of it.

The same-day drop contains a number of other applications carrying a Taiwan Semiconductor assignee that are independently concerned with reaching a source/drain from beneath the wafer. US20260206281A1 describes a back contact reaching into the source/drain through its back surface. US20260206291A1 describes two transistors given back-side contact plugs of deliberately different depths. US20260206290A1 describes back-side vias reaching source/drain regions with logic-device and memory-device vias at different depths. US20260206244A1 uses a buried etch stop and sacrificial epitaxial layers so a back-side via can land on the source/drain after substrate removal, and US20260206245A1 contacts one source/drain from both ends. US20260206217A1 splits a memory cell across both wafer faces. These records share a publication date and an assignee; nothing in any of them cross-references another, and none of them should be read as describing the hero's method. What can be said about the set without overreaching is narrow and worth saying anyway: several of these records presuppose that a contact will be built on the underside of a finished wafer, and the hero is the one whose claims address the thermal precondition for doing that — activating dopants at the back-side surface while the completed front side stays cold. As to whether any of it issues, and in what form, the file is silent. It published; that is the whole of the event.