Embedding non-volatile memory (NVM) on the same die as logic - rather than as a separate chip - saves area, power, and latency, but it means building two very different device types in one fabrication flow. Doing it with gate-all-around (GAA) logic, whose process is already complex, is harder still. International Business Machines Corporation's late-2020 grant claims that co-integration.
US10804274B2, "Co-integration of non-volatile memory on gate-all-around field effect transistor" (issued 2020-10-13), is classified in H01L 27/1052 (memory device integration) with H01L 21/8229 and H01L 29/0665. The claim's core is the co-integration - building NVM elements and GAA FETs together on one substrate.
Construe the integration limitation. NVM (whether charge-trap, floating-gate, or an emerging type) needs process steps - thick dielectrics, charge-storage layers - that can conflict with the delicate GAA channel-release flow. The claim fences a specific sequence that builds both without one ruining the other.
The design-around space is the integration scheme and the NVM type. A competitor using a different memory technology, or a different point in the flow to add the NVM, reaches embedded NVM-on-GAA outside this specific claim. The value is in IBM's particular route through a genuinely conflicting set of process requirements.
This is IBM Research again owning a hard integration problem ahead of volume - embedded NVM on advanced logic is a recurring customer ask (microcontrollers, secure elements, AI weight storage), and the GAA-era version of it is exactly the kind of forward-looking IP IBM accumulates for licensing.
For an R&D strategist, the grant signals that embedded-NVM-on-GAA has prior-art coverage from 2020, relevant to anyone planning eNVM at 3nm or below where GAA is the logic device.