Embedding non-volatile memory (NVM) on the same die as logic — rather than as a separate chip — saves area, power, and latency, but it means building two very different device types in one fabrication flow. Doing it with gate-all-around (GAA) logic, whose process is already complex, is harder still. International Business Machines Corporation's late-2020 grant claims that co-integration.

US10804274B2, "Co-integration of non-volatile memory on gate-all-around field effect transistor" (issued 2020-10-13), is classified in H01L 27/1052 (memory device integration) with H01L 21/8229 and H01L 29/0665. The claim's core is the co-integration — building NVM elements and GAA FETs together on one substrate.

“A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating…”— U.S. Patent No. 10,804,274 source

Construe the integration limitation, which is a precise process sequence rather than a general aspiration. Independent claim 1 is a method that begins with the two device regions sharing the same starting fins, then orchestrates a masked back-and-forth so each region gets its own treatment without disturbing the other. The recited steps: recess the fins in the channel region of both the NVM and the nanosheet FET to define source/drain; remove alternating portions of the recessed fins to open gaps; deposit an organic planarization layer (OPL) and a block mask to protect the FET; conformally deposit the NVM stack into the gaps over the NVM fins while the FET stays covered, leaving smaller second gaps; strip the OPL and block mask from the FET; deposit a fresh OPL and block mask to protect the NVM; and form the FET gate above and within the gaps while the NVM is shielded. The two protective-mask passes are the mechanism that lets two incompatible flows share one wafer.

The disclosed materials make the conflict concrete. The shared fins are alternating silicon and silicon-germanium (claim 5) — the same starting structure used to release GAA nanosheets — and claims 6 and 7 cover leaving either SiGe or Si above and below the gaps after the alternating-removal step. The NVM stack deposited into the gaps is itself a defined dielectric sandwich: silicon oxide nitride (claim 2), then hafnium dioxide on it (claim 3), then silicon dioxide on the hafnium dioxide (claim 4) — a charge-storage-capable stack conformally lining the recessed-fin gaps. Claim 9 then fills the remaining second gaps with polysilicon over the NVM stack, and claim 10 forms contacts to that polysilicon, while claim 8 forms contacts to the source/drain of both devices. These are the exact steps that would clash with a delicate nanosheet-release flow if run without the masking discipline claim 1 specifies.

The design-around space is the integration scheme and the NVM type. A competitor using a different memory technology, or adding the NVM stack at a different point in the flow, or protecting the two regions in a different masked order, reaches embedded NVM-on-GAA outside this specific claim. The value is in IBM's particular route — the dual OPL/block-mask hand-off and the hafnium-dioxide-based stack conformally deposited into shared-fin gaps — through a genuinely conflicting set of process requirements.

The specific dielectric stack is worth reading as the NVM's working layer. Silicon oxynitride, then hafnium dioxide, then silicon dioxide (claims 2—4) is a tunnel/charge-trap/block arrangement: the high-k hafnium dioxide acts as the charge-storage medium between thin oxide layers, deposited conformally so it lines the gaps opened in the recessed fins rather than sitting as a planar film. Conformality is the demanding part — the stack has to coat the inside of the alternating-layer gaps uniformly, which is why the claim specifies conformal deposition and a "second gap" left after the stack goes in, later filled with polysilicon (claim 9) to form the memory gate. Meanwhile the FET region, protected during all of this, gets its nanosheet channels released and a normal gate-all-around gate built in its own masked pass. The two devices therefore share fin formation, source/drain recessing, inner-spacer-style gap formation, and epitaxy, and diverge only in what fills the channel gaps — charge-storage stack for the NVM, wrap-around gate for the logic. That shared front end is precisely the area-and-cost argument for co-integration, and it is the part a freedom-to-operate analysis has to weigh against IBM's claim.

This is IBM Research again owning a hard integration problem ahead of volume — embedded NVM on advanced logic is a recurring customer ask (microcontrollers, secure elements, AI weight storage), and the GAA-era version of it is exactly the kind of forward-looking IP IBM accumulates for licensing.

For an R&D strategist, the grant signals that embedded-NVM-on-GAA has prior-art coverage from 2020, with a named process flow and material stack, relevant to anyone planning eNVM at 3nm or below where GAA is the logic device.

The CPC placement frames the contribution as memory-on-logic integration: H01L 27/1052 is the integration of memory devices, with H01L 21/8229 (bipolar/field-effect device manufacture) and H01L 29/0665 (semiconductor bodies with nanostructure channels, i.e. the nanosheet) supporting it. That is consistent with a method claim whose inventive step is the masked co-fabrication sequence rather than a novel memory cell or a novel transistor in isolation. Because the claims are method claims, the fence is the sequence of steps — the dual OPL/block-mask protection, the conformal hafnium-dioxide stack into shared-fin gaps, the polysilicon fill — so a competitor reads on the patent only by following materially the same ordered process, which is the practical question any eNVM-on-nanosheet roadmap has to answer against this 2020 priority.