Through-silicon vias (TSVs) - copper columns etched through a thinned silicon die to connect it vertically to another - are the structural prerequisite for high-bandwidth memory and most 3D integration. In 2020, before HBM became the defining bottleneck of the AI build-out, the TSV patent landscape was already crowded. Mapping the assignees that year tells you who was positioned for what came next.

Start with the foundry layer. Taiwan Semiconductor Manufacturing Co., Ltd.'s US10629592B2, "Through silicon via design for stacking integrated circuits" (issued 2020-04-21, CPC H01L 23/481 and H01L 24/89), claims a via design optimized for stacked ICs. TSMC's interest here is packaging-led: TSVs feed its interposer and stacking programs.

The memory makers owned the test-and-yield slice. Samsung Electronics Co., Ltd.'s US10580719B2 (issued 2020-03-03) claims analysis and correction of soft data failures across stacked chips - a reliability problem unique to vertically integrated DRAM. Micron Technology, Inc.'s US10797033B2 claims a high-sensitivity TSV resistance-measurement circuit, addressing the test challenge of verifying thousands of vias.

Then there is the system-integrator slice. Advanced Micro Devices, Inc.'s US10644826B2, "Flexible interfaces using through-silicon via technology" (issued 2020-05-05), claims a configurable TSV interface - AMD thinking about how a stacked memory talks to logic, foreshadowing its later 3D V-Cache work.

The facet data from the period confirms the concentration: Samsung, Intel, and Micron each held dozens of TSV-tagged grants, with TSMC and SK hynix close behind. The white space - where claims were sparse - sat in TSV thermal management and in fine-pitch via arrays below a few microns, which is exactly where the next round of innovation landed.

For a competitive-intelligence team, the 2020 map is a baseline. It shows that no single player could build an HBM stack without touching others' TSV claims, which is why cross-licensing and JEDEC-standard-essential patent pools became the operating norm in stacked memory.

The strategic read: foundries owned the via fabrication, memory makers owned the test and repair, and integrators owned the interface. That division of the thicket has largely persisted into the HBM3E era.