If you want to know whether a given AI accelerator needs a U.S. export license to ship to China, the answer no longer turns on what fab node printed it. It turns on two numbers buried in Export Control Classification Number (ECCN) 3A090: a 'total processing performance' (TPP) figure and a 'performance density' figure. The Bureau of Industry and Security (BIS) wrote those terms into the Commerce Control List because process geometry is a poor proxy for the thing the agency actually cares about, which is how much usable compute a part can deliver into a cluster. Reading the rule the way a classification engineer must read it, the controlling language is not the national-security narrative in the preamble; it is the parameter table.
What 3A090.a actually controls
The December 2024 BIS interim final rule restates ECCN 3A090.a as controlling integrated circuits having one or more digital processing units meeting either of two tests: a 'total processing performance' of 4800 or more, or a TPP of 1600 or more combined with a 'performance density' of 5.92 or more. That second prong matters as much as the first. It is the anti-circumvention clause. A vendor cannot simply ship a physically smaller, lower-aggregate-throughput die and assume it falls outside the control, because if that die packs its compute into a small enough area, the density prong sweeps it back in. TPP captures raw aggregate throughput; performance density captures throughput per unit of die area. Together they describe both 'how much compute' and 'how concentrated,' and a part has to clear both gates to escape 3A090.a.
This is a deliberate departure from how the Commerce Control List historically described high-performance computing, which leaned on metrics like adjusted peak performance. BIS retired that approach for AI accelerators because modern parts derive their value from dense, low-precision matrix throughput feeding large memory, not from double-precision floating point. TPP is computed from the bit operations a part can sustain across its processing units; performance density divides that by 'applicable die area,' which the rule measures in square millimeters and, per the technical note, includes the die area of any logic dies manufactured with a non-planar transistor architecture. The choice to measure die area, and to count only advanced-architecture logic die, tells you BIS is targeting leading-edge accelerators rather than legacy parts that happen to be large.
3A090.b: the band below the line
The same rule structure defines a lower control band. As later restated in the January 2025 AI Diffusion framework, ECCN 3A090.b controls integrated circuits having either a TPP of 2400 or more and less than 4800 combined with a performance density of 1.6 or more and less than 5.92, or a TPP of 1600 or more combined with a performance density of 3.2 or more and less than 5.92. The 3A090.b band exists so that the control surface is a continuum rather than a single cliff. A part that sits just under the 3A090.a thresholds does not drop into freedom; it lands in 3A090.b, which carries its own license requirements and license-exception eligibility. For anyone classifying a roadmap part, the practical takeaway is that you compute TPP and density first, then walk the part down the .a, .b, .z ladder.
The '.z' paragraphs are the catch for finished products. A consumer or networking chip that is controlled under another ECCN but also meets the 3A090 performance parameters gets a '.z' designation, which is how BIS reaches systems that embed controlled compute without re-describing every downstream product. The structure means the same accelerator silicon is reachable whether it ships as a bare die, a module, an add-in card, or inside a server, because the controlling characteristic travels with the compute, not with the form factor.
Why parameters, not nanometers
It is tempting to describe these rules as 'the chip controls' and assume they track a node number. They do not. A part fabricated on a mature process can, in principle, exceed the TPP threshold if it is large and parallel enough; a part on a bleeding-edge node can fall below it if it is small. By writing the control around computed performance and density, BIS made the rule node-agnostic and therefore harder to design around through pure process selection. The flip side is that classification now requires actually computing the parameters from a part's datasheet rather than reading a fab label, which is exactly why BIS maintains published guidance for how to calculate TPP and performance density and why these definitions live in technical notes attached to the ECCN rather than in the prose of the rule.
For compliance teams, the operational consequence is that 3A090 classification is a calculation, not a lookup. The two governing numbers are 4800 (the TPP ceiling for the top tier) and 5.92 (the performance-density figure that gates both the 3A090.a secondary prong and the top of the 3A090.b band), with 1600 and 2400 marking the lower TPP floors. Any part that touches those figures is a candidate for control, and any roadmap part designed to sit 'just under' the line has to clear the density test as well as the aggregate test to stay there. The rule is engineered so that there is no quiet gap between 'powerful enough to matter' and 'controlled.'
How 3A090 sits inside the broader Category 3 web
3A090 does not operate alone. The December 2024 rule revised it in the same amendatory package that touched ECCNs 3B001, 3B002, 3A090's related software entry 3D001, and its technology entry 3E001, among others, and BIS set a compliance date of December 31, 2024 for the bulk of those interlocking changes. The reason the entries move together is that the Commerce Control List controls a technology three ways at once: the commodity (3A090), the software needed to develop or use it (3D001 and related), and the technology to produce it (3E001 and related). A part that meets the 3A090 parameters therefore drags along controls on the software and technology that surround it, which is why an exporter cannot satisfy itself by classifying the silicon alone. The related computing items in ECCN 4A090, covering computers and assemblies that incorporate or are built around 3A090 ICs, extend the same parameter logic up the integration stack so that a server is reachable on the strength of the accelerators inside it.
There is one more subtlety in how die area is counted, and it is easy to misread. The technical note to 3A090 specifies that 'applicable die area' for the performance-density calculation includes all die area of logic dies manufactured with a process node that uses a non-planar transistor architecture. That qualifier is doing targeting work: it focuses the density metric on parts built with modern FinFET or gate-all-around-class transistors rather than older planar logic. The effect is that a chiplet design stitching together multiple advanced-architecture logic dies has its density computed across the relevant die area, so disaggregating an accelerator into chiplets does not by itself dilute the figure that controls it. Once again the drafting anticipates the obvious design-around and forecloses it inside the definition rather than chasing it later.