The transition to gate-all-around (GAA) is not all-or-nothing. GAA gives the best channel control but at the cost of extra process complexity, so there is a case for using GAA only where its electrostatics matter and keeping cheaper FinFET devices elsewhere on the same die. Taiwan Semiconductor Manufacturing Co., Ltd.'s mid-2022 grant claims a structure that does exactly that.
US11328960B2, "Semiconductor structure with gate-all-around devices and stacked FinFET devices" (issued 2022-05-10), is classified in H01L 21/823431 (CMOS integration) with H01L 29/78696 (GAA), H01L 29/66545, and H01L 27/0886 (FinFET). The claim's novelty is the co-integration - GAA and stacked FinFET devices coexisting in one structure on one substrate.
“An integrated circuit includes a stacked FinFET in a second area and a GAA transistor in a first area.”— U.S. Patent No. 11,328,960 source
Construe why co-integration is hard and therefore claimable. GAA and FinFET have different channel formations, different gate processes, and different thermal budgets. Building both on one wafer without one process step ruining the other device type is a real integration challenge, and the claim fences a specific way to do it.
The limitation that matters is the structural arrangement that lets both device types share a fabrication flow. The independent claim pins down how the GAA region and the FinFET region are formed relative to each other - which is the only thing a competitor must avoid to design around it.
The strategic logic is cost-and-performance partitioning. A designer could put GAA in the speed-critical logic and FinFET (or stacked FinFET) in less-demanding blocks, optimizing area and cost per function. The patent defends TSMC's route to offering that flexibility.
For a portfolio analyst, this co-integration claim signals that TSMC is thinking past a clean GAA cutover toward heterogeneous device-type chips. It is the kind of transitional IP that matters most during a node-architecture handoff, and it sits alongside TSMC's pure-GAA and forksheet filings as part of a deliberately broad device-architecture position.