The transition to gate-all-around (GAA) is not all-or-nothing. GAA gives the best channel control but at the cost of extra process complexity, so there is a case for using GAA only where its electrostatics matter and keeping cheaper FinFET devices elsewhere on the same die. Taiwan Semiconductor Manufacturing Co., Ltd.'s mid-2022 grant claims a structure that does exactly that.

US11328960B2, "Semiconductor structure with gate-all-around devices and stacked FinFET devices" (issued 2022-05-10), is classified in H01L 21/823431 (CMOS integration) with H01L 29/78696 (GAA), H01L 29/66545, and H01L 27/0886 (FinFET). The claim's novelty is the co-integration — GAA and stacked FinFET devices coexisting in one structure on one substrate.

“An integrated circuit includes a stacked FinFET in a second area and a GAA transistor in a first area.”— U.S. Patent No. 11,328,960 source

Construe why co-integration is hard and therefore claimable. GAA and FinFET have different channel formations, different gate processes, and different thermal budgets. The clever part of independent claim 1 is that the two devices start from the same stack of alternately deposited semiconductor layers — silicon and silicon-germanium, per claim 4 — and then diverge in how the gate is formed. In the FinFET region the gate dielectric and electrode are formed over the top and sidewalls of the intact stack, so both the silicon and SiGe layers remain and the silicon layers electrically connect the source/drain. In the GAA region the SiGe is removed and the gate dielectric wraps fully around the suspended silicon nanosheets. One starting fin, two finished device types.

That shared-fin origin is the load-bearing limitation, and the method claims walk it step by step. Claim 11 recites providing fins in both areas, etching source/drain trenches, partially recessing the SiGe to open gaps, forming inner spacer features in those gaps, and epitaxially growing the source/drain — all common to both regions — before a first etch mask exposes only the FinFET area so its sacrificial gate is replaced with a dielectric over the intact fin. Claim 13 then covers a second mask over the FinFET area, removing the SiGe in the GAA region to suspend the silicon layers, and wrapping a gate dielectric around each. Several dependents capture the subtle structural tells of building both at once: claim 8 has the FinFET gate dielectric thicker than the GAA one (claim 15 forms it that way), claim 3 notes that a first-region silicon layer at the same stack level can be thicker in its middle than its GAA counterpart, and claim 10 has the FinFET fin wider than the GAA nanosheet stack.

The strategic logic is cost-and-performance partitioning, and the claims even tag where each device belongs. Claim 9 places the GAA in a core area and the stacked FinFET in an I/O area — exactly the split a designer would want, since I/O transistors often run at higher voltage and tolerate a thicker gate dielectric and the simpler FinFET channel, while the core gets GAA's superior electrostatics. The spacer materials are spelled out too (claim 6: low-k, silicon oxide, nitride, oxynitride, carbide, oxycarbide, or oxycarbonitride), and claim 5 has both device types share the same spacer dielectric, reinforcing that this is one integrated flow rather than two bolted together.

The two method-side independent claims, 11 and 16, differ in a detail that matters for scope. Both start from fins of alternating first and second semiconductor materials in the two areas, etch source/drain trenches, partially recess the second layers to open gaps, fill those gaps with inner spacer features, and epitaxially grow source/drain — claim 19 names the inner-spacer materials and claim 20 fixes the layers as epitaxial silicon and silicon-germanium. The divergence is sequencing: claim 11 etches the two fins' trenches in nominally separate recitations (claim 12 then notes the two etches are done by the same process), while claim 16 etches both fins together and forms the FinFET gate dielectric and electrode before turning to the GAA region. Claim 18 adds the most specific timing constraint — the second (GAA) gate electrode is formed after the source/drain epitaxy but before the first etch mask is laid down. These ordering limitations are the real fence: a competing flow that releases the GAA nanosheets and forms its gate at a different point relative to the masking and epitaxy steps falls outside them even if the finished die also mixes wrapped-gate and fin-gate transistors.

The design-around space is the integration scheme. A competitor that builds its GAA and FinFET regions from separate fin stacks, or sequences the gate replacement differently, reaches a mixed-device die outside a claim that turns on the shared alternating-layer fin and the two-mask gate divergence. The value is precisely TSMC's route to forming both from one starting structure without one process step ruining the other device.

The classification underscores that this is a CMOS-integration patent first and a device patent second. The lead code H01L 21/823431 is the integration of CMOS devices, with H01L 29/78696 (the gate-all-around nanowire/nanosheet device), H01L 29/66545 (replacement-gate processing), and H01L 27/0886 (the FinFET) hanging off it. That ordering matches the claims: the novelty the office credited is not GAA alone or FinFET alone — both are prior art — but the integrated flow that yields one of each from a shared starting fin via a two-mask, replacement-gate sequence. For anyone planning a node where the I/O transistors stay on a thicker-oxide, simpler device while the core moves to nanosheets, this is the kind of claim to read before committing to a particular masked-divergence flow.

For a portfolio analyst, this co-integration claim signals that TSMC is thinking past a clean GAA cutover toward heterogeneous device-type chips. It is the kind of transitional IP that matters most during a node-architecture handoff, and it sits alongside TSMC's pure-GAA and forksheet filings as part of a deliberately broad device-architecture position.