What does a through-silicon-via patent actually claim once you read past the title? For Taiwan Semiconductor Manufacturing (TSMC), the hero record in this week's grant drop, US12667018B2 ("Semiconductor device including multi-dimension through silicon via structures for backside alignment and thermal dissipation," issued June 23, 2026), claims something more specific than "a via through a chip." Its load-bearing idea is that vias of different widths in the same 3D-IC do different jobs at once: a wider columnar via delivers power and conducts heat out of the stack, while a narrower via with lower electrical capacitance carries signals — and the pattern of those vias is reused as an alignment mark for joining die backside to backside. This is an issued, granted patent, not a pending application; the claim language below is scope an examiner has allowed, classified under the H10W 90/00 region for three-dimensional integrated-circuit devices (the reorganized home of the former H01L25 stacked-device territory).

Read independent claim 1 element by element, because the scope lives in the limitations, not the abstract. It recites a method: forming, within a substrate, a first columnar structure with a first set of properties tied to a first rate of thermal conduction for a temperature difference; forming, above the substrate, a seal ring structure interspersed within dielectric layers, where the first columnar structure has a side adjacent to or underlying that seal ring; and forming, adjacent to the first columnar structure, a second columnar structure with a lesser rate of thermal conduction, on the opposite side of the first structure. The thermal-conduction asymmetry between the two adjacent vias is the limitation doing the work — claim 1 does not merely claim two vias, it claims two vias whose differing thermal-conduction rates and positions relative to a seal ring are recited explicitly. The dependent chain then anchors timing (the first via formed before or after the integrated circuitry, before or after the seal ring) and, in claim 7, adds joining the substrate to another substrate "using a direct alignment technique" that includes "using a vision system to detect the first columnar structure."

The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.— Semiconductor device including multi-dimension through silicon via structures for backside alignment and thermal dissipation, US12667018B2

The two device claims, 8 and 14, are where the dual-width idea becomes geometric and where the width ratio surfaces as an explicit number. Claim 8 recites a substrate with stacked first, second, and third dielectric layers, a seal ring interspersed in the second layers, and two columnar structures penetrating into the substrate on opposite sides of the seal ring — one whose top surface reaches the plane of the substrate's upper surface, the other reaching the plane of the upper third dielectric layer, again with a lesser thermal-conduction rate. Its dependents make the structure concrete: claim 12 recites the first via as "approximately rectangular" from a top view; claim 13 recites a pattern of columnar structures "configured to be detectable by a vision system of a semiconductor processing tool" — the alignment-mark function, now claimed in the device rather than the method. Claim 14 introduces a three-via arrangement, and claim 19 recites a third via with a width lesser than the first two. Claim 20 then pins a ratio: "a ratio of a greater width... to a lesser width... is greater than or equal to approximately 5:3." A bounded width ratio like 5:3 is the kind of numeric limitation that defines where the dependent coverage begins.

Why one via doing three jobs is the claimed idea

In a conventional 3D-IC, signal TSVs want to be narrow — narrow copper means lower parasitic capacitance and cleaner high-speed signaling — while power delivery and heat extraction want fat, low-resistance, high-thermal-mass conductors. Those are competing geometries, and a die that needs both has historically placed separate structures for each. The granted patent's framing is that the same multi-dimension via array can host both: the abstract describes the first (narrow) columnar structure as low-capacitance and "configured for electrical signaling," and the second (wide) columnar structure as "configured to provide power" and to "conduct heat... for thermal management." Reusing the wider via's pattern "for alignment purposes" folds a third function — backside-to-backside die registration — onto the same features. For a claim reader the consequence is navigational: the independent claims are directed to via structures distinguished by paired thermal-conduction rates and position relative to a seal ring, with width and alignment functions recited in the dependents.

Where it sits in the grant-day cluster and the CPC map

The hero does not arrive alone. TSMC's June 23, 2026 grant drop includes a run of advanced-packaging and 3D-integration patents in adjacent serial numbers, which is what makes this a portfolio read rather than a one-off. US12667020B2 ("Hybrid underfill structures for multi-die packages and methods of forming the same") claims a multi-die package combining a non-conductive film between one die and the substrate with a capillary underfill around a second die, plus a multi-die frame forming a single multi-die chip — the mechanical-and-thermal interface layer that stacked and side-by-side dies require. Issued in the same window, US12667000B2, US12666998B2, US12666997B2, US12666979B2, and US12666968B2 sit in the same device-and-method packaging neighborhood. Read together, the cluster describes the connective tissue of multi-die integration from several angles at once: vias, underfill, frames, and the routing between stacked dies.

On classification, the hero's main CPC neighborhood is H10W 90/00 — the 3D-IC and through-silicon-via territory in the reorganized H10W space for semiconductor device assemblies, which is where IP readers should now look for what the legacy H01L25 stacked-device and H01L23 interconnect groups used to cover. The signal in that placement is consistent with the claims: a patent whose independent claims recite vias penetrating a substrate, a seal ring interspersed in dielectric layers, and backside alignment is, by construction, filed into the 3D-integration corner of the map rather than the front-end transistor subclasses. The seal-ring limitation in particular is telling — claims 1, 8, and 14 each position the columnar structures relative to a seal ring, the peripheral guard structure that protects a die's active area, which situates these vias near the die edge where backside alignment marks and edge-routed power are most useful.

What the record shows, and what it does not

The factual summary is deliberately narrow. The assignee is Taiwan Semiconductor Manufacturing (TSMC). The hero, US12667018B2, issued June 23, 2026 as a granted patent, claims a multi-dimension TSV structure for a 3D-IC: independent method claim 1 and independent device claims 8 and 14 recite adjacent columnar vias of differing thermal-conduction rates flanking a seal ring, with dependents reciting a rectangular via cross-section, a vision-detectable alignment pattern, and a greater-to-lesser width ratio of at least approximately 5:3. The abstract identifies the narrow via as low-capacitance signaling and the wide via as power delivery and heat conduction, with the via pattern reused for alignment. The companion grants in the same drop are directed to multi-die underfill, frames, and related packaging structures. That is the coverage these records describe.

What the record does not show is worth stating plainly. The width ratio, the seal-ring positioning, and the paired thermal-conduction limitations are what the patent claims, not findings about which TSMC products practice them or how broadly the claims read against competitors. This is an issued patent, so the scope is allowed scope rather than merely sought scope — but allowed is not the same as enforced, valuable, or commercially deployed, none of which the public claim record speaks to. For an IP reader tracking TSMC's 3D-integration thicket, the value of a grant-day read is exactly this: it shows, in the assignee's own now-issued claim language, that TSMC holds a claimed structure in which a single via array is built to carry power, move heat, and register stacked die — down to a 5:3 width ratio.