Integrated fan-out (InFO) is one of the reasons advanced packaging became a competitive moat rather than a commodity step. Instead of mounting a die on a separate package substrate, fan-out embeds the die in a molded reconstituted wafer and builds the routing — the redistribution layers — directly on top, fanning the fine die pads out to coarser board pitch. Taiwan Semiconductor Manufacturing Company, Ltd. has built this into a portfolio engineered for breadth, and the June 2026 grants show the layering clearly.
The routing layer comes first. US12653074B2, "Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device" (issued 2026-06-09), is the keystone. Its title alone recites three things — UBM structure, RDL design, and an integrated passive device — and its classifications mix H10W packaging classes with H01G 4/00 (capacitors). This is a claim on building passives into the fan-out routing, which is how you eliminate discrete components and shrink the module. It fences the most value-dense layer of the package.
The assembled structure comes second. US12653061B2, "Package structure and method of manufacturing the same" (2026-06-09), claims the package as a built object plus its fabrication method. The dual structure-and-method form is deliberate portfolio engineering: a structure claim catches the competitor who ships the package, and the method claim catches the competitor who builds it, even via a different facility. Holding both closes the obvious workaround of "we make it differently."
The materials layer comes third. US12653036B2, "Semiconductor device and method" (2026-06-09), is classified with polymer/dielectric classes (C08G 73/1025, C09D 179/08 — polyimide-class chemistry) alongside the H10W packaging classes. This is the dielectric and bonding chemistry that the RDL is built in. Owning the dielectric method underneath the routing is owning a layer every fan-out flow must use, regardless of the routing topology on top.
Profile the three together and the architecture of the moat is visible: TSMC is not holding one broad fan-out patent (which would be easy to design around and easy to challenge) — it is holding a stack of narrower claims that each cover a different layer of the same package. RDL-with-passives, the assembled structure, and the dielectric chemistry. A competitor can design around any single one; designing around all three simultaneously, while still shipping a cost-competitive fan-out package, is the actual barrier.
For a competitive-intelligence read, this is the difference between a fence and a wall. A fence is one patent you route around. A wall is a layered portfolio where every plausible route touches a different claim. TSMC's June 2026 fan-out grants are a wall, and any entrant's freedom-to-operate analysis has to clear the RDL layer, the package layer, and the dielectric layer separately.