The densest known way to build CMOS is the complementary FET (CFET): stack the n-type transistor directly on top of the p-type, sharing the footprint instead of placing them side by side. Applying that to SRAM - the cell that scales worst and gates every node's area claim - is a high-value target. International Business Machines Corporation's mid-2025 grant claims a stacked-FET SRAM.
US12328859B2, "Stacked FET SRAM" (issued 2025-06-10), is classified tightly in a single CPC: H10B 10/125 (SRAM device structures, the H10B successor to the older SRAM codes). The narrow classification signals a focused device-structure claim - this is about the SRAM cell built from stacked FETs, not a broad process.
“A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor.”— U.S. Patent No. 12,328,859 source
Construe the stacked-FET limitation in the SRAM context. A six-transistor SRAM cell has a fixed transistor count; the only way to shrink it further once layout tricks are exhausted is to stack devices vertically. The claim turns on how the cell's pull-up, pull-down, and pass-gate transistors are arranged in a stacked (CFET-style) configuration. That arrangement is the fenced element.
The design-around space is the device topology. A competitor using planar-arranged GAA SRAM, or a different vertical-stacking scheme, reaches an SRAM cell outside a claim tied to this specific stacked-FET arrangement. CFET-based SRAM is itself one of several post-GAA memory-density paths.
IBM Research's role here is consistent with its history: it pioneered much of the GAA and CFET device work and patents the cell-level applications early. Stacked-FET SRAM is a research-to-near-production concept, and IBM's claim is a priority-date marker in a field where Intel, TSMC, and imec are all pursuing CFET.
For an R&D strategist, this grant is a signal that SRAM scaling is moving into the vertical-stacking era, and that IBM holds early cell-structure IP there. Given that SRAM area is the single most-cited node-scaling metric, stacked-FET SRAM claims are among the most strategically loaded in the device portfolio.