The useful thing about reading a company's publications as a set rather than one at a time is that the set tells you something the individual record cannot. On July 16, 2026, fifty-two US applications published carrying a Huawei assignee: forty-nine under HUAWEI TECHNOLOGIES CO., LTD., two under Huawei Digital Power Technologies Co., Ltd., and one under Huawei Cloud Computing Technologies Co., Ltd. — three distinct assignee strings that should not be collapsed into one another. Sorted by subject matter, the shape of that group is unmistakable and unsurprising: wireless and 5G communications, antennas, handset interaction, foldable hinges, displays, health and wearables, and neural-network software. That is the portfolio Huawei publishes week after week.

One record does not belong to it. US20260206566A1, titled STATIC RANDOM-ACCESS MEMORY ARRAY, MEMORY, AND ELECTRONIC DEVICE, is the only memory, transistor, or semiconductor-device record among the fifty-two. It is an A1 publication — a pending application, not an issued patent, and not a thing Huawei has been "awarded." Its priority chain is specific and worth stating exactly: it is a continuation of PCT/CN2024/097127, filed June 3, 2024, claiming priority to CN 202311183082.3, filed September 13, 2023. Its CPC assignments are H10W 20/2128, H10B 10/12, and H10W 20/435. Six inventors are named — Weiliang Jing, Shihui Yin, Xiaoxuan Zhao, Ying Wu, Zhengbo Wang, and Heng Liao — and the record establishes their presence on the filing and nothing else about them.

What claim 1 actually recites

Claim 1 is an apparatus claim and it has four elements: a semiconductor substrate; a front-end-of-line device layer; a back-end-of-line device layer; and a plurality of memory cells. The geometry between the layers is recited, not left to inference — the FEOL layer is disposed in the substrate, and the BEOL layer is disposed on the FEOL layer. Then comes the assignment that gives the claim its content: each memory cell comprises at least one P-type field-effect transistor and at least one N-type field-effect transistor; the PFET is formed in the front-end-of-line device layer; the NFET is formed in the back-end-of-line device layer. That is the whole of the independent claim. It says nothing about cell topology, nothing about the process by which the BEOL device is built, and nothing about performance. Notice, too, what claim 1 does not say. It does not say the two transistors sit on top of one another. "In the BEOL layer" and "in the FEOL layer" locate them on different levels; they do not require the levels to line up. The vertical overlap arrives in claim 2, which recites that an orthographic projection of the NFET on the semiconductor substrate at least partially overlaps an orthographic projection of the PFET on the substrate. Claim 2 is dependent, which means the word "stacked" — the word every reader will reach for — is licensed by a narrower claim than the one at the top of the record. There are twenty claims in all.

The application's BACKGROUND lays out why the arrangement is being proposed, and it is the familiar SRAM-scaling wall. A standard six-transistor bit cell puts all six devices side by side in the substrate, so the cell's footprint is the sum of the six. But the six have different demands on them — per the record, the pull-down transistor carries the highest turn-on performance requirement, the access transistor the next, the pull-up transistor the lowest — and transistor size drives turn-on performance. Shrink them uniformly to buy density and the performance goes with it:

Therefore, the sizes of the transistors are strictly limited, and the sizes cannot be further reduced with miniaturization of a process node. Consequently, improvement of the memory density of the SRAM is limited.— STATIC RANDOM-ACCESS MEMORY ARRAY, MEMORY, AND ELECTRONIC DEVICE, US20260206566A1

That is the applicant characterizing the prior art, not an independent finding, and it is the setup for the role split the SUMMARY describes: the NFET, serving as the pull-down transistor with the highest turn-on requirement, is the one made by the back-end-of-line process; the PFET, serving as the pull-up transistor with the lowest requirement, stays front-end-of-line. The SUMMARY asserts that at the same process node this keeps pull-down performance while integrating more cells per unit area, and puts a figure on the area: a memory cell's vertical projection region can be reduced to 2/N of an existing structure's, with N left undefined in that passage. That is an applicant's assertion in a summary section, not a measured benchmark, and the record contains no fabrication data or measured results of any kind. On cell topology the record is also not quite of one mind: the abstract offers a 6T or 8T cell as examples, while the SUMMARY additionally mentions a 3T cell.

A portfolio with no neighbors

Here is where the set-level reading earns its keep, and where the honest answer is a negative one. A filing like this ordinarily arrives surrounded by relatives — process records, array-architecture records, peripheral-circuit records — and the cluster tells you something about how serious and how staffed the effort is. This one has none. Among the fifty-two records, there is no second silicon-device filing to pair it with. The nearest hardware-adjacent publications are adjacent only in the loosest sense: US20260205142A1 is a forward-error-correction encoder framed as a chip; US20260206396A1 is a display drive backplane bonded to an epitaxial wafer, wafer-bonding work aimed at microLED rather than logic or memory; US20260202631A1 is an optical-module package. None of them is a transistor or memory record, and none should be read as related art.

There is one trap in the drop worth naming so nobody else falls into it. US20260203175A1 surfaces on any keyword search for "memory" in this set — but it is a cloud-service record about hot-standby virtual-machine failover using memory shared across hosts. The memory there is datacenter RAM in the systems sense, not a memory device. Pairing it with the hero would manufacture a cluster of two out of a cluster of one. Same for US20260203563A1 and US20260203582A1, both AI-software records — quantization and training-schedule work — that share a drop with the hero and nothing else.

So the observation stands on its own, unpadded: a single SRAM-device application, drawn from a Chinese priority filing dated September 2023 and a 2024 PCT, published into a Huawei week otherwise composed entirely of radios, screens and software. What that isolation means is not in the record, and this brief will not pretend otherwise. The scope is the scope — claim 1 puts the PFETs below and the NFETs above; claim 2 makes them overlap — and it is pending.